IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 59

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
PHY-to-Controller Interfaces
Figure 6–12. Word-Aligned Writes
Notes to
(1) To show the even alignment of afi_cs_n, expand the signal (this convention applies for all other signals).
(2) The afi_dqs_burst must go high one memory clock cycle before afi_wdata_valid. Compare with the word-unaligned case.
(3) The afi_wdata_valid is asserted two afi_wlat controller clock (afi_clk) cycles after chip select (afi_cs_n) is asserted. The afi_wlat
(4) Observe the ordering of write data (afi_wdata). Compare this to data on the mem_dq signal.
(5) In all waveforms a command record is added that combines the memory pins ras_n, cas_n and we_n into the current command that is issued.
December 2010 Altera Corporation
indicates the required write latency in the system. The value is determined during calibration and is dependant upon the relative delays in the
address and command path and the write datapath in both the PHY and the external DDR SDRAM subsystem. The controller must drive afi_cs_n
and then wait afi_wlat (two in this example) afi_clks before driving afi_wdata_valid.
This command is registered by the memory when chip select (mem_cs_n) is low. The important commands in the presented waveforms are WR
= write, ACT = activate.
afi_wdata_valid
afi_dqs_burst
mem_cs_n
Figure
command
(Note 5)
mem_dqs
afi_cas_n
afi_wdata
afi_ras_n
afi_we_n
mem_clk
mem_dq
afi_cs_n
Memory
Interface
afi_addr
afi_wlat
afi_clk
6–12:
11 11
11 11
11 11
00 00
2
01
00 00
00000000
00000000
00000000
00000000
ACT
ACT
00 00
Note 1
11
10
03020100
01
Note 2
11
11
07060504
Note 3
Note 4
10
00
11
00
00
Section IV. RLDRAM II Controller with UniPHY IP User Guide
0b0a0908
0020008
11
11
WR
External Memory Interface Handbook Volume 3
11
0f0e0d0c
00
6–19