IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 27
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IPR-RLDII/UNI
Manufacturer Part Number
IPR-RLDII/UNI
Description
IP CORE Renewal Of IP-RLDII/UNI
Manufacturer
Altera
Datasheet
1.IP-RLDIIUNI.pdf
(76 pages)
Specifications of IPR-RLDII/UNI
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Arria II GZ, Stratix III, Stratix IV, HardCopy III
Core Architecture
FPGA
Core Sub-architecture
Arria, HardCopy, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
Chapter 2: Getting Started
Generated Files
Table 2–9. Generated Directory Structure and Key Files—Qsys Synthesis Flow (Part 2 of 2)
Table 2–10. Generated Directory Structure and Key Files—Qsys Verilog Simulation
Table 2–11. Generated Directory Structure and Key Files—Qsys VHDL Simulation
December 2010 Altera Corporation
<working_dir>/<system_name>/
synthesis/submodules/
Note to
(1) <stamp> is a unique identifier created by Qsys during generation.
<working_dir>/<system_name>/
sim_verilog/
<working_dir>/<system_name>/
sim_verilog/submodules/
<working_dir>/<system_name>/
sim_verilog/submodules/
<working_dir>/<system_name>/
sim_verilog/submodules/
<working_dir>/<system_name>/
sim_verilog/submodules/
<working_dir>/<system_name>/
sim_verilog/submodules/
Note for
(1) <stamp> is a unique identifier created by Qsys during generation.
<working_dir>/<system_name>/
sim_vhdl/
<working_dir>/<system_name>/
sim_vhdl/submodules/
<working_dir>/<system_name>/
sim_vhdl/submodules/
<working_dir>/<system_name>/
sim_vhdl/submodules/
Note to
(1) <stamp> is a unique identifier created by Qsys during generation.
Table 2–9
Table
Table
Directory
Directory
Directory
2–11:
2–10:
Verilog Simulation
Table 2–10
simulation flow with Qsys.
VHDL Simulation
Table 2–11
simulation flow with Qsys.
lists the generated directory structure and key files created by the VHDL
Other IP core files
lists the generated directory structure and key files created by the Verilog
<system_name>.v
<core_name>_<stamp>.v
<core_name>_<stamp>_*.v
<core_name>_<stamp>_*.sv
<core_name>_<stamp>_readme.txt
Other IP core files
<system_name>.vhd
<core_name>_<stamp>.vho
<core_name>_<stamp>_*.vhd
<core_name>_<stamp>_*.vho
vhdl_files.txt
File Name
File Name
File Name
(1)
(1)
(1)
Section IV. RLDRAM II Controller with UniPHY IP User Guide
External Memory Interface Handbook Volume 3
Other IP core files.
Qsys system top-level wrapper.
UniPHY top-level wrapper.
UniPHY Verilog RTL files.
UniPHY SystemVerilog RTL
files.
Readme text file.
Other IP core files.
Qsys system top-level wrapper.
UniPHY VHDL top-level module.
UniPHY VHDL simulation files.
File list text file.
Description
Description
Description
2–17