IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 38

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–2
User-Controlled Features
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Write Data FIFO Buffer
Command Issuing FSM
Refresh Timer
Timer Module
AFI
f
■
The write data FIFO buffer accepts write data from the Avalon-MM interface. The AFI
controls the subsequent consumption of the FIFO buffer write data.
The command issuing finite-state machine (FSM) has three states. The controller is in
the INIT state when the PHY initializes the memory. Upon receiving the
afi_cal_success signal, the state transitions to INIT_COMPLETE. If the calibration fails,
afi_cal_fail is asserted and the state transitions to INIT_FAIL. The PHY receives
commands only in the INIT_COMPLETE state.
When a refresh request arrives at the state machine at the same time as a read or write
request, the refresh request takes precedence. The read or write request waits until
there are no more refresh requests, and is issued immediately if timing requirements
are met.
With automatic refresh, the refresh timer periodically issues refresh requests to the
command issuing FSM. The refresh interval can be set at generation.
The timer module contains one DQ timer and eight bank timers (one per bank). The
DQ timer tracks how often read and write requests can be issued, to avoid bus
contention. The bank timers track the cycle time (t
The 8-bit wide output bus of the bank timer indicates to the command issuing FSM
whether each bank can be issued a read, write, or refresh command.
For information on the AFI, refer to
The following features are available on the General Settings tab of the parameter
editor. These features are disabled by default.
The second part is the burst divider in the front end of the Avalon-MM interface,
which breaks long Avalon bursts into individual requests of sequential addresses,
which then pass to the controller state machine.
“Functional Description—UniPHY” on page
RC
Chapter 5: Functional Description—Controller
).
December 2010 Altera Corporation
User-Controlled Features
6–1.