IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 64

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–2
Example Driver
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Read and Write Generation
The example driver for Avalon-MM memory interfaces generates Avalon-MM traffic
on an Avalon-MM master interface. As the read and write traffic is generated, the
expected read response is stored internally and compared to the read responses as
they arrive. If all reads report their expected response, the pass signal is asserted;
however, if any read responds with unexpected data a fail signal is asserted.
Each operation generated by the driver is a single write or block of writes followed by
a single read or block of reads to the same addresses, which allows the driver to
precisely determine the data that should be expected when the read data is returned
by the memory interface. The driver comprises a traffic generation block, the
Avalon-MM interface and a read comparison block. The traffic generation block
generates addresses and write data, which are then sent out over the Avalon-MM
interface. The read comparison block compares the read data received from the
Avalon-MM interface to the write data from the traffic generator. If at any time the
data received is not the expected data, the read comparison block records the failure,
finishes reading all the data, and then signals that there is a failure and the driver
enters a fail state. If all patterns have been generated and compared successfully, the
driver enters a pass state.
Within the driver, there are the following main states:
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Within each of the generation states there are the following substates:
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For each of the states and substates, the order and number of operations generated for
each substate is parameterizable — you can decide how many of each address pattern
to generate, or can disable certain patterns entirely if you want. The sequential and
random interleave substate takes in additions to the number of operations to generate.
An additional parameter specifies the ratio of sequential to random addresses to
generate randomly.
The traffic generator block can perform individual or block read and write generation.
Individual Read and Write Generation
During the individual read and write generation stage of the driver, the traffic
generation block generates individual write followed by individual read Avalon-MM
transactions, where the address for the transactions are chosen according to the
specific substate. The width of the Avalon-MM interface is a global parameter for the
driver, but each substate can have a parameterizable range of burst lengths for each
operation.
Generation of individual read and writes
Generation of block read and writes
The pass state
The fail state
Sequential address generation
Random address generation
Mixed sequential and random address generation
Chapter 7: Functional Description—Example Top-Level Project
December 2010 Altera Corporation
Example Driver