IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 44
IPR-RLDII/UNI
Manufacturer Part Number
IPR-RLDII/UNI
Description
IP CORE Renewal Of IP-RLDII/UNI
Manufacturer
Altera
Datasheet
1.IP-RLDIIUNI.pdf
(76 pages)
Specifications of IPR-RLDII/UNI
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Arria II GZ, Stratix III, Stratix IV, HardCopy III
Core Architecture
FPGA
Core Sub-architecture
Arria, HardCopy, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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6–4
Figure 6–3. Write Datapath
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
DQSn
DQS
Write Datapath
DQ[n-1]
DQ[0]
ALTIOBUF
The write datapath passes write data from the memory controller to the I/O. The DQ
pins are bidirectional and shared between read and write. The write data valid signal
from the memory controller generates the output enable signal to control the output
buffer. It also generates the dynamic termination control signal, which selects between
series (output mode) and parallel (input mode) termination. An ALT_OCT
megafunction (instantiated in the top-level file) configures the termination values.
Figure 6–3
is sent to a DDIO_OUT cell. The output of ALTDQ_DQS feeds an ALTIOBUF buffer
which creates a pair of pseudodifferential clocks that connects to the memory. In
full-rate mode, only the SDR-DDR portion of the ALTDQ_DQS logic is used; in
half-rate mode, the HDR-SDR circuitry is also required. The
<variation_name>_pin_assignments.tcl script automatically specifies the logic option
that associates all DQ pins to the DQS pin. The Fitter treats the pins as a DQS/DQ pin
group.
ALTDQ_DQS
SDR DDR
DDIO_OUT
illustrates the write datapath. The full-rate PLL output clock phy_mem_clk
DDIO_OUT
DDIO_OUT
n-1
0
HDR SDR
DDIO_OUT
DDIO_OUT
DDIO_OUT
DDIO_OUT
2n-2
2n-1
1
0
Chapter 6: Functional Description—UniPHY
December 2010 Altera Corporation
wdata[4n-4]
wdata[4n-3]
wdata[4n-2]
wdata[4n-1]
wdata[0]
wdata[1]
wdata[2]
wdata[3]
vcc
phy_mem_clk
phy_afi_clk
phy_mem_write_clk
gnd
wdata[4n-1:0]
Block Description
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