IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 6

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–2
Features
General Description
8B10B Encoder/Decoder MegaCore Function User Guide
Table 1–2. Device Family Support (Part 2 of 2)
The following list summarizes the features of the 8B10B Encoder/Decoder MegaCore
function:
■
■
■
■
■
■
Encoders and decoders are used for physical layer coding for Gigabit Ethernet, Fibre
Channel, and other applications. The 8b/10b encoder takes byte inputs, and generates
a direct current (DC) balanced stream (equal number of 1s and 0s) with a maximum
run length of 5. Some of the individual 10-bit codes will have an equal number of 1s
and 0s, while others will have either four 1s and six 0s, or, six 1s and four 0s. In the
latter case, the disparity between 1s and 0s is used as an input to the next 10-bit code
generation, so that the disparity can be reversed, and maintain an overall balanced
stream. For this reason, some 8-bit inputs have two valid 10-bit codes, depending on
the input disparity.
The Altera 8B10B Encoder/Decoder is a compact, high performance MegaCore
function capable of encoding and decoding in multi-gigabit applications.
Device Family
Cyclone IV GX
HardCopy
HardCopy III
HardCopy IV (E, GX)
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
Stratix IV
Other device families
8b/10b encoding and decoding.
Cascaded encoding and decoding.
Industry compatible special character coding.
Easy-to-use IP MegaWizard
Support for OpenCore Plus evaluation.
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators.
®
®
II
Preliminary
™
interface.
Support
Preliminary
Full
Preliminary
Preliminary
Full
Full
Full
Full
Full
Preliminary
No support
Chapter 1: About This MegaCore Function
© November 2009 Altera Corporation
Features