IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 15

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
8B10B Encoder /Decoder Walkthrough
Set Constraints
© November 2009 Altera Corporation
Table 2–1
directory. The names and types of files specified in the summary vary based on
whether you created your design with VHDL or Verilog HDL.
Table 2–1. Generated Files
The 8B10B Encoder/Decoder MegaCore function variations include a tool command
language (Tcl) script. Use this Tcl script to constrain your design.
To run the Tcl script in the Quartus II software, in a Win32 operating system, follow
either of these sets of steps:
1. Select TCL Scripts (Tools menu).
2. Select the applicable Tcl file for your variation:
3. Click Run.
<variation name>.bsf
<variation name>.cmp
<variation name>.html
<variation name>.v
<variation name>.vo
<variation name>_bb.v
<variation name>_constraints.tcl
<variation name>_enc8b10b.ocp
<variation name>_enc8b10b.v
<variation name>_run_modelsim.tcl
<variation name>_tb.v
Notes to
(1) These files are variation dependent, some may be absent or their names may change.
(2) <variation name> is a prefix variation name supplied automatically by the MegaWizard interface.
(3) If you choose the decoder mode, the file name is <variation name>_dec8b10b.
<variation name>_constraints. tcl
or
Table
describes the generated files and other files that may be in your project
Filename
2–1:
(2)
(Note 1)
Preliminary
Quartus II symbol file for the MegaCore function
variation. You can use this file in the Quartus II block
diagram editor.
VHDL component declaration file
The MegaCore function report file.
A MegaCore function variation file, which defines a
Verilog HDL top-level description of the custom
MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling
your design in the Quartus II software.
Verilog HDL IP functional simulation model.
Verilog HDL black-box file for the MegaCore function
variation. Use this file when using a third-party EDA tool
to synthesize your design.
Tool command language (tcl) script used to set
constraints.
An OpenCore Plus file, needed for time-limited or tethered
hardware evaluation.
Verilog HDL RTL for this MegaCore function variation.
A Tcl script to automate the process of running the
provided demo testbench with the IP functional
simulation model.
A Verilog HDL module with the top-level demo testbench
for the core.
8B10B Encoder/Decoder MegaCore Function User Guide
Description
2–5