IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 17

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Compile the Design
Compile the Design
Program a Device
© November 2009 Altera Corporation
1
In all cases, the testbench is in Verilog HDL, therefore a license to run mixed language
simulations is required to run the testbench with the VHDL model.
Altera recommends that you disable the auto-ROM replacement feature in the
Quartus II software. Enabling this feature produces a smaller but slower MegaCore
function.
You can use the Quartus II software to compile your design. Refer to Quartus II Help
for instructions on compiling your design.
After you have compiled your design, program your targeted Altera device, and
verify your design in hardware.
Preliminary
8B10B Encoder/Decoder MegaCore Function User Guide
2–7