IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 16

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–6
Simulate the Design
IP Functional Simulation Model
8B10B Encoder/Decoder MegaCore Function User Guide
f
f
1
4. Click on Tcl Console under Utility_Windows (View menu).
5. In the Tcl console window, type:
To run the Tcl script in a UNIX or Linux operating system terminal, type:
Depending on the type of constraints applied by the Tcl script, analysis and synthesis
may be run twice. For example, if hierarchy independent constraints are needed, the
Tcl script runs analysis and synthesis before applying the constraints. Therefore, when
you run a full compilation, after running the Tcl script, the analysis and synthesis are
run a second time.
You can now integrate your custom MegaCore function variation into your design,
simulate, and compile.
You can simulate your design using the generated VHDL and Verilog HDL IP
functional simulation models.
For more information on IP functional simulation models, refer to the
Altera IP in Third-Party Simulation Tools
Altera also provides a Verilog HDL demonstration testbench, including scripts to
compile and run the demonstration testbench using a variety of simulators and
models. This testbench demonstrates the typical behavior of an 8B10B MegaCore
function, and how to instantiate a model in a design. The demonstration testbench
does not perform any error checking.
For a complete list of models or libraries required to simulate the 8B10B
Encoder/Decoder MegaCore function, refer to the _run_modelsim.tcl scripts
provided with the demonstration testbench.
To use the demonstration testbench with IP functional simulation models in the
ModelSim
1. Start the ModelSim simulator.
2. From the ModelSim File menu, use Change Directory to change the working
3. In the ModelSim Transcript window, execute the command
source <variation name>_constraints.tcl
cd..<project_directory>
quartus_sh -t <variation name>_constraints.tcl
directory to the directory where you created your 8B10B Encoder/Decoder
variation.
do <variation_name>_run_modelsim.tcl which sets up the required
libraries, compiles the netlist files, and runs the testbench. The ModelSim
Transcript window displays messages from the testbench reflecting the results of
the simulation.
®
simulator, follow these steps:
Preliminary
chapter in Volume 3 of the Quartus II Handbook.
© November 2009 Altera Corporation
Chapter 2: Getting Started
Simulating
Simulate the Design