IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 23

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Specifications
Functional Description
Figure 3–4. Cascaded Encoding
Note to
(1) The ena, idle_ins, and rdforce signals are set high (logic 1).
© November 2009 Altera Corporation
Figure
3–4:
Encoding Latency
When the register inputs/outputs parameter is turned on, the encoder is pipelined,
thus it takes three clock cycles for a character to be encoded. The encoded value—
corresponding to the values of datain and kin sampled by the encoder on rising
edge n—is output shortly after rising edge n+2, and is available to be sampled on the
rising edge of clock cycle n+3. (See
encoding, the data paths fed by the rdforce and rdin inputs are not pipelined.
Because rdforce and rdin are normally only used in cascaded configurations, this
should not be a problem. In cases where the rdforce and rdin inputs are to be used
in noncascaded configurations, they should be delayed two clock cycles with respect
to their corresponding datain and kin values.
When the register inputs/outputs parameter is turned off, the encoder takes one clock
cycle to encode a character. The encoded value—corresponding to the values of
datain and kin sampled by the encoder on rising edge n—is output shortly after
rising edge n, and is available to be sampled on the rising edge of clock cycle n+1.
(See
datain
kin
Figure
[15:0]
[1:0]
3–6).
clk
reset_n
kin [1]
ena
idle_ins
rdin
rdforce
clk
reset_n
kin [0]
ena
idle_ins
datain [7:0]
rdin
rdforce
datain [15:8]
Preliminary
Figure 3–5 on page
8B10B Encoder/Decoder MegaCore Function User Guide
kerr
dataout [19:10]
valid
rdout
rdcascade
kerr
dataout [9:0]
valid
rdout
rdcascade
3–6). To enable cascaded
3–5