IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 24

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–6
Decoder
8B10B Encoder/Decoder MegaCore Function User Guide
Figure 3–5. Encoder Timing Diagram—Three Cycle Latency
Figure 3–6. Encoder Timing Diagram—One Cycle Latency
Fibre Channel and IEEE 802.3z 1000BaseX
In Fibre Channel and IEEE 802.3z 1000BaseX applications the encoder does not
automatically select the correct 8-bit data for Fibre Channel EOF or 1000BaseX Idle
ordered sets. The running disparity based selection of the correct 8-bit data must be
made before passing the data to the encoder.
Data and identified 10-bit special K codes are converted from 10 bits to 8 bits; see
Table 3–1 on page 3–3
illustration of the conversion process.
When special 10-bit K codes are received, the special K codes are translated to 8-bit
values, and the kout signal is asserted. The decoder also checks for invalid 10-bit
codes.
When the decoder receives an invalid code, it asserts the kerr signal and decodes the
value to an arbitrary number.
When the idle_del signal is asserted, it deletes all 10-bit words identified as the
special IDLE character of K28.5.
When the receiver detects a disparity error, the rderr signal is asserted.
1
The decoder flags the 10B_ERR characters as invalid codes and asserts the
kerr signal.
dataout, rdout, kerr, valid
dataout, rdout, kerr, valid
datain, kin, en, idle_ins
datain, kin, en, idle_ins
for a list of the valid K codes, and
rdforce, rdin
rdforce, rdin
rdcascade
rdcascade
Preliminary
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clk
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Figure 3–1 on page 3–1
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© November 2009 Altera Corporation
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Chapter 3: Specifications
Functional Description
for an