IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 22

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–4
8B10B Encoder/Decoder MegaCore Function User Guide
The encoder encodes invalid characters in the same way it encodes Idle (K28.5) codes.
The decoder treats invalid characters as Idle codes.
Figure 3–3
Figure 3–3. Encoder
Disparity
The running disparity can be forced to positive or negative, allowing the user to insert
a special resynchronization pattern, or disparity errors.
When the rdforce input is asserted, the value on the rdin port is assumed to be the
current running disparity. Setting rdin to 0 forces the encoder to produce an encoded
word with positive or neutral disparity. Setting rdin to 1 forces the encoder to
produce an encoded word with negative or neutral disparity.
Cascaded Encoding
Two encoders can be cascaded to allow for 16-bit word encoding. The encoders are
cascaded by connecting the rdcascade output of the most significant byte (MSByte)
encoder to the rdin input of the least significant byte (LSByte) encoder, and by
connecting the rdout output of the LSByte encoder to the rdin input of the MSByte
encoder. These connections ensure proper running disparity computation. The
rdforce inputs must be asserted (active high) for the encoders to take into account
the value on the rdin inputs, rather than use their internally generated running
disparity. Both ena inputs must be high or low at the same time. The kin [1] signal
relates to datain[15:8], and kin[0] relates to datain[7:0].
page 3–5
If the encoded words are to be transmitted serially, the result of encoding
datain[15:8] should be transmitted first.
shows two encoders connected together to perform cascaded encoding.
shows a block diagram of the encoder.
datain [7:0]
Preliminary
reset_n
idle_ins
rdforce
ena
rdin
clk
kin
© November 2009 Altera Corporation
kerr
dataout [9:0]
valid
rdout
rdcascade
Figure 3–4 on
Chapter 3: Specifications
Functional Description