DP83865DVH National Semiconductor, DP83865DVH Datasheet - Page 8

• Manufacturer Part Number: DP83865DVH
• Description: 10/100/1000BASE-T TRANSCEIVER, SMD
• Manufacturer: National Semiconductor

Specifications of DP83865DVH

• Data Rate: 1000Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u, IEEE 802.3z
• Supply Current: 430µA
• Supply Voltage Range: 2.375V To 2.625V, 3.135V To 3.465V
• Operating Temperature Range: 0°C To +70°C
• Interface Type: GMII, MII, RGMII
• Rohs Compliant: Yes
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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1.0 Pin Description
1.5 Clock Interface
1.6 Device Configuration and LED Interface
(See section “3.7 PHY Address, Strapping Options and LEDs” on page 45 and section “5.9 LED/Strapping Option” on
page 67.)
TCK
CLK_IN
CLK_OUT
CLK_TO_MAC
NON_IEEE_STRAP
MAN_MDIX_STRAP /
TX_TCLK
Signal Name
Signal Name
Signal Name
I/O,
S, PD
I/O,
S, PD
Type
Type
Type
(Continued)
O
O
I
I
PQFP
PQFP
PQFP
PIn #
Pin #
Pin #
24
86
87
85
1
6
TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test
logic input and output controlled by the testing entity.
This pin should be left floating if not used.
CLOCK INPUT: 25 MHz oscillator or crystal input (50 ppm).
CLOCK OUTPUT: Second terminal for 25 MHz crystal. Must be left floating if
a clock oscillator is used.
CLOCK TO MAC OUTPUT: This clock output can be used to drive the clock
input of a MAC or switch device. This output is available after power-up and is
active during all modes except during hardware or software reset. Note that the
clock frequency is selectable through CLK_MAC_FREQ between 25 MHz and
125 MHz.
To disable this clock output the MAC_CLK_EN_STRAP pin has to be tied low.
NON IEEE COMPLIANT MODE ENABLE: This mode allows interoperability
with certain non IEEE compliant 1000BASE-T transceivers.
‘1’ enables IEEE compliant operation and non-compliant operation
‘0’ enables IEEE compliant operation but inhibits non-compliant operation
Note: The status of this bit is reflected in bit 10 of register 0x10. This pin also
sets the default for and can be overwritten by bit 9 of register 0x12.
MANUAL MDIX SETTING: This pin sets the default for manual MDI/MDIX
configuration.
‘1’ PHY is manually set to cross-over mode (MDIX)
‘0’ PHY is manually set to straight mode (MDI)
Note: The status of this bit is reflected in bit 8 of register 0x10. This pin also
sets the default for and can be overwritten by bit 14 of register 0x12.
TX_TCLK: TX_TCLK is enabled by setting bit 7 of register 0x12. It is used to
measure jitter in Test Modes 2 and 3 as described in IEEE 802.3ab specifica-
tion. TX_TCLK should not be confused with the TX_CLK signal. See Table 12
on page 29 regarding Test Mode setting. This pin should be left floating if not
used.
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Description
Description
Description