DP83865DVH National Semiconductor, DP83865DVH Datasheet - Page 54

• Manufacturer Part Number: DP83865DVH
• Description: 10/100/1000BASE-T TRANSCEIVER, SMD
• Manufacturer: National Semiconductor

Specifications of DP83865DVH

• Data Rate: 1000Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u, IEEE 802.3z
• Supply Current: 430µA
• Supply Voltage Range: 2.375V To 2.625V, 3.135V To 3.465V
• Operating Temperature Range: 0°C To +70°C
• Interface Type: GMII, MII, RGMII
• Rohs Compliant: Yes
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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4.0 Functional Description
1000 Mbps Mode Transmit Path Timing
In the transmit path, the TX signals are the output of the
MAC and input of the PHY. The MAC output has a data to
clock skew of -500 ps to +500 ps in both HP and 3COM
mode. The PHY input, on the receiver side, requires data
to clock input skew between 1.0 ns to 2.6 ns. To meet the
minimum data skew of 1.0 ns at the PHY input while the
MAC output skew is at -500 ps (i.e., the worst case), the
clock signal (RGMII_TCK) needs to be delayed by minu-
mum of 1.5 ns. To meet the maximum data skew of 2.6 ns
at the PHY input while MAC output skew is at +500 ps, the
maximum clock delay (RGMII_TCK) needs to be within 2.1
ns.
The 3COM mode clock delay is implemented internal in the
DP83865DVH. The HP or 3COM mode can be selected at
register 0x12.13:12.
1000 Mbps Mode Receive Path Timing
In the data receive path, the RX signals are the output of
the PHY and input of the MAC. The PHY output has a data
to clock skew of -500 ps to +500 ps (i.e., the HP mode).
If the MAC input, on the receiver side, is operating in
3COM mode that requires minimum of 1.0 ns setup time,
the clock signal (RGMII_RX_CLK) needs to be delayed
with minimum of 1.5 ns if the PHY output has a data to
clock skew of -500 ps. The 3COM mode requires the MAC
input has a minimum hold time of 0.8 ns. Meeting the
3COM minimum input hold time, the maximum clock signal
delay while PHY output skew is at +500 ps would be 2.3
ns.
The 3COM mode clock delay is implemented internal in the
DP83865DVH. The HP or 3COM mode can be selected at
register 0x12.13:12.
4.6.3 10/100 Mbps Mode
When RGMII interface is working in the 100 Mbps mode,
the Ethernet Media Independent Interface (MII) is imple-
mented by reducing the clock rate to 25 MHz. For 10 Mbps
operation, the clock is further reduced to 2.5 MHz. In the
RGMII 10/100 mode, the transmit clock RGMII_TX_CLK is
generated
RGMII_RX_CLK is generated by the PHY. During the
packet receiving operation, the RGMII_RX_CLK may be
stretched on either the positive or negative pulse to accom-
modate the transition from the free running clock to a data-
synchronous clock domain. When the speed of the PHY
changes, a similar stretching of the positive or negative
pulses is allowed. No glitch is allowed on the clock signals
during clock speed transitions.
This interface will operate at 10 and 100 Mbps speeds the
same way it does at 1000 Mbps mode with the exception
that the data may be duplicated on the falling edge of the
appropriate clock.
The MAC will hold RGMII_TX_CLK low until it has ensured
that it is operating at the same speed as the PHY.
4.7 10BASE-T and 100BASE-TX Transmitter
The 10BASE-T and 100BASE-TX transmitter consists of
several functional blocks which convert synchronous 4-bit
nibble data, as provided by the MII, to a 10 Mb/s MLT sig-
nal for 10BASE-T operation or scrambled MLT-3 125 Mb/s
by
the
MAC
and
the
(Continued)
receive
clock
54
serial data stream for 100BASE-TX operation. Since the
10BASE-T and 100BASE-TX transmitters are integrated
with the 1000BASE-T, the differential output pins, TD+ /-
are routed to channel A of the AC coupling magnetics.
The block diagram in Figure 6 provides an overview of
each functional block within the 10BASE-T and 100BASE-
TX transmit section. The Transmitter section consists of the
following functional blocks:
10BASE-T:
— NRZ to Manchester Encoder
— Link Pulse Generator
— Transmit Driver
— Jabber Detect
100BASE-TX:
— Code-group Encoder and Injection block
— Parallel-to-Serial block
— Scrambler block
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / DAC / Line Driver
In 10BASE-T mode the transmitter meets the IEEE 802.3
specification Clause 14.
The DP83865 implements the 100BASE-X transmit state
machine diagram as specified in the IEEE 802.3u Stan-
dard, Clause 24.
4.7.1 10BASE-T Manchester Encoder
The encoder begins operation when the Transmit Enable
input (TXE) goes high. The encoder converts the clock and
NRZ data to Manchester data for the transceiver. For the
duration of TXE remaining high, the Transmit Data (TXD) is
encoded for the transmit differential driver. TXD must be
valid on the rising edge of Transmit Clock (TXC). Transmis-
sion ends when TXE goes low. The last transition is always
positive; it occurs at the center of the bit cell if the last bit is
a one, or at the end of the bit cell if the last bit is a zero.
4.7.2 Link Pulse Generator
The link generator is a timer circuit that generates a normal
link pulse (NLP) as defined by the 10 Base-T specification
in 10BASE-T mode. The pulse which is 100ns wide is
transmitted on the transmit output, every 16ms, in the
absence of transmit data. The pulse is used to check the
integrity of the connection to the remote MAU.
4.7.3 Transmit Driver
The 10 Mb/s transmit driver in the DP83865 shares the
100/1000 Mb/s common driver.
4.7.4 Jabber Detect
The Jabber Detect function disables the transmitter if it
attempts to transmit a much longer than legal sized packet.
The jabber timer monitors the transmitter and disables the
transmission if the transmitter is active for greater than 20-
30ms. The transmitter is then disabled for the entire time
that the ENDEC module's internal transmit is asserted. The
transmitter signal has to be deasserted for approximately
400-600ms (the unjab time) before the Jabber re-enables
the transmit outputs.
Jabber status can be read from BMSR 0x01.1. For 100
Mb/s and 1000 Mb/s operations, Jabber Detect function is
not incorporated so that BMSR 0x01.1 always returns “0”.