DP83865DVH National Semiconductor, DP83865DVH Datasheet - Page 64

• Manufacturer Part Number: DP83865DVH
• Description: 10/100/1000BASE-T TRANSCEIVER, SMD
• Manufacturer: National Semiconductor

Specifications of DP83865DVH

• Data Rate: 1000Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u, IEEE 802.3z
• Supply Current: 430µA
• Supply Voltage Range: 2.375V To 2.625V, 3.135V To 3.465V
• Operating Temperature Range: 0°C To +70°C
• Interface Type: GMII, MII, RGMII
• Rohs Compliant: Yes
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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5.0 Design Guide
between the ground and VDD plane also minimizes EMI
radiation.
Any through-hole clock oscillator component should be
mounted as flat and as close to the PCB as possible.
Excessive leads should be trimmed. Provide a ground pad
equal or larger than the oscillator foot print on the compo-
nent side of the PCB. Tie this ground pad to the ground
plane through multiple vias. This minimizes the distance to
the ground plane and provide better coupling of the electro-
magnetic fields to the board.
5.3 Power Supply Decoupling
The capacitance between power and ground planes can
provide appreciable power supply decoupling for high edge
rate circuits. This "plane capacitor" has very low ESR and
ESL so that the plane capacitance remains effective at the
frequencies so high that chip capacitors become ineffec-
tive. It is strongly recommended that the PC board have
one solid ground plane and at least one split power plane
with 2.5V and 1.8V copper islands. Ideally the PCB should
have solid planes for each of the supply voltages. The
interplane capacitance between the supply and ground
planes may be maximized by reducing the plane spacing.
In addition, filling unused board areas on signal planes with
copper and connecting them to the proper power plane will
also increase the interplane capacitance.
The 2.5V and the 1.8V supply pins are paired with their cor-
responding ground pins. Every other paired supply pins
need to be decoupled with Surface Mount Technology
(SMT) capacitors.
tance alternates between 0.01 F and 0.1
resonance frequencies of the capacitors are "dispersed".
The decoupling capacitors should be placed as close to the
supply pin as possible. For optimal results, connect the
decoupling capacitors directly to the supply pins where the
capacitors are placed 0.010 inch to the power pins. For
lowest ESL and best manufacturability, place the plane
connecting via within 0.010 inch to the SMT capacitor pads
(Figure 14).
Bulk capacitance supplies current and maintains the volt-
age level at frequencies above the rate that the power sup-
ply can respond to and below frequencies chip capacitors
are effective. To supply lower speed transient current, a
tantalum 10 F capacitor for each power plane and each
port should also be placed near the DP83865.
Lowering the power supply plane and ground plane imped-
ance will also reduce the power supply noise. 1 oz. copper
is recommended for the power and ground planes. Avoid
routing power or ground traces to the supply pins that could
< 10 mil
Figure 14. Place via close to pad.
Decoupling capacitor pad
It’s recommended that SMT capaci-
Via
(Continued)
< 10 mil
Via to plane
F so that the
64
introduce inductive coupling leading to ground bounce.
Connect power and ground pins directly to the planes.
The power supply decouping recommendations may be
perceived conservative. However, for the early prototyp-
ing, please follow the guide lines and recommendations to
assure first time success. To lower the manufacturing cost,
the component count may be reduced by the designer after
careful evaluation and extensive tests on EMI and bit-error-
rate (BER) performance.
5.4 Sensitive Supply Pins
The Analog 1V8_AVDD2 and 1V8_AVDD3 supply are sus-
ceptible to noise and requires special filtering to attenuate
high frequencies. A low pass filter for each of the supply pin
is suggested (Figure 15).
A 1% 9.76 k resistor is needed to connect to the BG_REF
pin. The connections to this resistor needs to be kept as
short as possible (Figure 15).
Avoid placing noisy digital signal traces near these sensi-
tive pins. It is recommended that the above mentioned
components should be placed before other components.
The 1.8V supplies both the digital core and the analog.
The analog power supply is sensitive to noise. To optimize
the analog performance, it is best to locate the voltage reg-
ulator close to the analog supply pins. Avoid placing the
digital core supply and GMAC in the analog return path.
An example of voltage regulator placement is shown in
Figure 16.
Ferrite beads could be used to isolate noisy VCC pins and
preventing noise from coupling into sensitive VCC pins.
This bead in conjunction with the bypass capacitors at the
VCC pins form a low pass filter that prevents the high fre-
quency noise from coupling into the quiet VCC. However,
the use of ferrite beads may yield mixed results when the
inductance resonates with the capacitance. To decrease
the likelihood of resonance, a resistor in parallel with the
ferrite bead may be used. The noise characteristics vary
from design to design. Ferrite beads may not be effective
in all cases. The decision is left to the board designer
based on the evaluation of a specific case.
5.5 PCB Layer Stacking
To route traces for the DP83865 PQFP package, a mini-
mum of four PCB layers is necessary. To meet perfor-
mance requirements, a six layer board design is
recommended. The following is the layer stacking recom-
mendations for four and six-layer boards.
Four-layer board (typical application: NIC card):
1. Top layer - signal
2. GND
3. 3.3 Volt power plane
4. Bottom layer - signal, planes for 1.8 Volt and 2.5 Volt
Six-layer board:
1. Top layer - signal
2. 2.5 Volt power plane
3. GND
4. 1.8 Volt power plane
5. Power plane for IO_VDD and/or 3.3 Volt
6. Bottom layer - signal
Note that signal traces crossing a plane split should be
avoided (Figure 17). Signal crossing a plane split may
cause unpredictable return path currents and would likely