©2002 National Semiconductor Corporation
General Description
The DP83865 is a fully featured Physical Layer transceiver
with integrated PMD sublayers to support 10BASE-T,
100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83865 is an ultra low power version of the DP83861
and DP83891. It uses advanced 0.18 um, 1.8 V CMOS
technology, fabricated at National Semiconductor’s South
Portland, Maine facility.
The DP83865 is designed for easy implementation of
10/100/1000 Mb/s Ethernet LANs. It interfaces directly to
Twisted Pair media via an external transformer. This device
interfaces directly to the MAC layer through the IEEE
802.3u Standard Media Independent Interface (MII) or the
IEEE 802.3z Gigabit Media Independent Interface (GMII).
The DP83865 is a fourth generation Gigabit PHY with field
proven architecture and performance. Its robust perfor-
mance ensures drop-in replacement of existing 10/100
Mb/s equipment with 10/100/1000 Mb/s networking infra-
structure.
Applications
The DP83865 fits applications in:
System Diagram
PHYTER
DP83865BVH Gig PHYTER
10/100/1000 Ethernet Physical Layer
10/100/1000 Mb/s capable node cards
Switches with 10/100/1000 Mb/s capable ports
High speed uplink ports (backbone)
®
is a registered trademark of National Semiconductor Corporation.
10/100/1000 Mb/s
ETHERNET MAC
DP83820
MII
GMII
crystal or oscillator
ETHERNET PHYSICAL LAYER
25 MHz
®
10/100/1000 Mb/s
V
DP83865
Features
Fully compliant with IEEE 10BASE-T, 100BASE-TX and
1000BASE-T specifications (802.3u, 802.3z, 802.3ab).
Integrated PMD sublayer featuring adaptive equalization
and baseline wander compensation according to ANSI
X3.T12.
3.3 V or 2.5 V MAC interfaces:
– IEEE 802.3u MII
– IEEE 802.3z GMII
User programmable GMII pin ordering.
IEEE 802.3u Auto-Negotiation and Parallel Detection
– Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s,
LED support for activity, full / half duplex, link1000,
link100 and link10 or user programmable (manual
on/off).
Supports 25 MHz operation with crystal or oscillator.
Requires only two power supplies, 1.8 V (core and ana-
log) and 2.5 V (analog and I/O). 3.3V is supported as an
alternative supply for I/O voltage.
User programmable interrupt.
Supports Auto-MDIX at 10, 100 and 1000 Mb/s.
Supports JTAG (IEEE1149.1).
Ultra low power consumption of one watt typical.
Management port (MDC / MDIO).
128-pin PQFP package (14mm x 20mm).
WOL support.
and 10 Mb/s full duplex and half duplex devices
STATUS
LEDs
ADVANCED INFORMATION
10BASE-T
100BASE-TX
1000BASE-T
September 2002
RJ-45
www.national.com