MB9BF104RPMC-GE1 Fujitsu Semiconductor America Inc, MB9BF104RPMC-GE1 Datasheet - Page 82
MB9BF104RPMC-GE1
Manufacturer Part Number
MB9BF104RPMC-GE1
Description
IC MCU 32BIT 256KB FLASH 120LQFP
Manufacturer
Fujitsu Semiconductor America Inc
Series
FM3 MB9B100r
Datasheets
1.MB9BF104NPMC-G-JNE1.pdf
(100 pages)
2.MB9BF104NPMC-G-JNE1.pdf
(4 pages)
3.MB9BF104RPMC-GE1.pdf
(1 pages)
Specifications of MB9BF104RPMC-GE1
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
80MHz
Connectivity
CSIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
100
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
120-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
865-1117
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL
*3 : A high-speed mode I
*4 : t
82
MB9B100 Series
SCL clock frequency
(Repeated) START condition
hold time
SDA SCL
SCLclock "L" width
SCLclock "H" width
(Repeated) START setup time
SCL SDA
Data hold time
SCL SDA
Data setup time
SDA SCL
STOP condition setup time
SCL SDA
Bus free time between
"STOP condition" and
"START condition"
Noise filter
(12) I
SDA
SCL
indicates the power supply voltage of the pull-up resistance and I
signal.
satisfies the requirement of "tSUDAT ≥ 250 ns".
CYCP
2
C timing
is the peripheral clock cycle time. To use I
tHDSTA
Parameter
tLOW
2
C bus device can be used on a standard mode I
tHDDAT
Symbol
tHDDAT
tHDSTA
tSUDAT
tSUSTA
tSUSTO
tHIGH
tLOW
tBUF
fSCL
tSUDAT
tSP
tHIGH
Conditions
R = (Vp/I
CL = 50pF,
(*1)
2
C, set the peripheral bus clock at 8 MHz or more.
tSUSTA
-
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40C to + 85C)
OL
)
tHDSTA
2 t
Min Max Min Max
(*4)
250
4.0
4.7
4.0
4.7
4.0
4.7
CYCP
Typical
0
0
mode
OL
indicates V
2
C bus system as long as the device
3.45
(*2)
100
-
-
-
-
-
-
-
-
2 t
High-speed
tSP
(*4)
100
0.6
1.3
0.6
0.6
0.6
1.3
CYCP
0
0
OL
mode
guaranteed current.
(*3)
400
0.9
DS706-00007-1v0-E
-
-
-
-
-
-
-
-
tSUSTO
Unit Remarks
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
tBUF