LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 8

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-3. Slice Diagram
Table 2-1. Slice Signal Descriptions
1. See Figure 2-2 for connection details.
2. Requires two PFUs.
Function
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
From
Routing
Control Signals
selected and
inverted per
slice in routing
Note: some interslice
signals not shown.
Inter-PFU signal
Inter-PFU signal
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Data signals
Data signals
Data signals
Data signals
Data signal
Data signal
Type
CLK
LSR
M1
M0
CE
C1
D1
C0
D0
A1
B1
A0
B0
Signal Names
A0, B0, C0, D0 Inputs to LUT4
A1, B1, C1, D1 Inputs to LUT4
Q0, Q1
F0, F1
OFX0
OFX1
FCO
LSR
CLK
FCI
FCI into Different Slice/PFU
M0
M1
FCO from Different Slice/PFU
CE
FCO from Slice/PFU,
FCI into Slice/PFU,
LUT4 &
CARRY
LUT4 &
CARRY
CO
CO
CI
CI
Multipurpose Input
Multipurpose Input
Clock Enable
Local Set/Reset
System Clock
Fast Carry In
LUT4 output register bypass signals
Register Outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT8
For the right most PFU the fast carry chain output
F
F
2-4
OFX0
1
Expansion
LUT
Mux
Slice
LatticeSC/M Family Data Sheet
D
D
Description
Latch
Latch
2
FF/
FF/
MUX depending on the slice
OFX1
F1
Q1
OFX0
F0
Q0
2
To
Routing
Architecture