LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 243

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
September 2007
November 2007
December 2008
January 2008
January 2010
March 2008
June 2008
Date
Version
01.7
01.8
01.9
02.0
02.1
02.2
02.3
Ordering Information
Ordering Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Characteristics
Supplemental
Supplemental
Architecture
Architecture
Architecture
Introduction
Introduction
Information
Information
Section
Multiple
—
Added Thermal Management text section.
Updated title list.
Removed -7 speed grade information for 115K LUT devices in the
Ordering Information tables.
Corrections/Additions to memory controller list (Tables 1-2).
AIL Overview – Modified power used by AIL block.
PURESPEED I/O Buffer Banks – Modified VTT termination info. Added
info about complimentary drivers for all banks.
Supported Source Synchronous Interfaces – Modified data for DDRII in
Table 2-11.
Recommended Operating Conditions – Changed footnote 3.
Initialization and Standby Supply Current – Inserted a paragraph with
info regarding the table. Also updated the table.
Typical Building Block Function Performance – Added
VCC=1.2V=1.2V+/-5% above Pin to Pin Performance table.
LatticeSC External Switching Characteristics – Added
VCC=1.2V=1.2V+/-5% above table. Reworded footnote 3.
LatticeSC Family Timing Adders – Added VCC=1.2V=1.2V+/-5% above
table.
LatticeSC Internal Timing Parameters – Added VCC=1.2V=1.2V+/-5%
above table. Reworded footnote 1.
GSR Timing – Added a new table for Internal System Bus Timing after
GSR Timing.
LatticeSC sysCONFIG Port Timing – Corrected sysCONFIG SPI Port
information.
Signal Descriptions – Modified info for VTT_x, PROBE_VCC, and
PROBE_GND. Modified info for [LOC]_DLL[T,C]_IN[C,D,E,F].
Updated list of technical notes, added reference to LatticeSC/M 
flexiPCS Data Sheet.
Updated Internal Timing Parameters table.
Updated Read Mode timing diagram.
Updated Read Mode with Input Registers Only timing diagram.
Data sheet status changed from preliminary to final.
Removed Read-Before-Write sysMEM EBR mode.
Updated LatticeSC/M External Switching Characteristics table.
Updated LatticeSC/M Internal Timing Parameters table.
Removed Read-Before-Write sysMEM EBR mode.
Output/Tristate DDR/Shift Register Block Diagram - corrected connec-
tion to POS.
DC and Switching Characteristics table - updated data for t
Added T
Characteristics (LVDS) table.
Removed references to HyperTransport throughout the data sheet.
Updated per PCN #01A-10 (ceramic fcBGA conversion to organic
fcBGA for the 1152-ball and 1704-ball fcBGA packages) and PCN
#02A-10 (1020-ball organic fcBGA conversion to 1020-ball organic
fcBGA revision 2 package).
7-5
R,
T
F
parameter to PURESPEED I/O Differential Electrical
Change Summary
LatticeSC/M Family Data Sheet
Revision History
SUI_PIO.