LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 2

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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January 2010
Features
High Performance FPGA Fabric
4 to 32 High Speed SERDES and flexiPCS™
(per Device)
2Gbps High Performance PURESPEED™ I/O
Memory Intensive FPGA
• 15K to 115K four input Look-up Tables (LUT4s)
• 139 to 942 I/Os
• 700MHz global clock; 1GHz edge clocks
• Performance ranging from 600Mbps to 3.8Gbps
• Excellent Rx jitter tolerance (0.8UI at
• Low Tx jitter (0.25UI typical at 3.125Gbps)
• Built-in Pre-emphasis and equalization
• Low power (typically 105mW per channel)
• Embedded Physical Coding Sublayer (PCS) 
• Supports the following performance bandwidths
• 144 Tap programmable Input Delay (INDEL)
• Electrical standards supported:
• Programmable On Die Termination (ODT)
• sysMEM™ embedded Block RAM
3.125Gbps)
provides pre-engineered implementation for the
following standards:
block on every I/O dynamically aligns data to
clock for robust performance
– GbE, XAUI, PCI Express, SONET, Serial Rapi-
– Differential I/O up to 2Gbps DDR 
– Single-ended memory interfaces up to
– Dynamic bit Adaptive Input Logic (AIL) mon-
– Dynamic bus: uses control bus from DLL
– Static per bit
– LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL
– SSTL 3/2/18 I, II; HSTL 18/15 I, II
– PCI, PCI-X
– LVDS, Mini-LVDS, Bus-LVDS, MLVDS,
– Includes Thevenin Equivalent and low
dIO, 1G Fibre Channel, 2G Fibre Channel
(1GHz Clock)
800Mbps
itoring and control circuitry per pin that auto-
matically ensures proper set-up and hold
LVPECL, RSDS
power V
TT
termination options
LatticeSC/M Family Data Sheet
1-1
sysCLOCK™ Network
Masked Array for Cost Optimization
(MACO™) Blocks
High Performance System Bus
System Level Support
• Additional 240K to 1.8Mbits distributed RAM
• Eight analog PLLs per device
• 12 DLLs per device with direct control of I/O
• Extensive clocking network
• Precision Clock Divider
• Dynamic Clock Select (DCS)
• On-chip structured ASIC Blocks provide pre-
• Ties FPGA elements together with a standard
• IEEE standard 1149.1 Boundary Scan, plus 
• IEEE Standard 1532 in-system configuration
• 1.2V and 1.0V operation
• Onboard oscillator for initialization and general
• Embedded PowerPC microprocessor interface
• Low cost wire-bond and high pin count flip-chip
• Low cost SPI Flash RAM configuration
delay
engineered IP for low power, low cost system
level integration
bus framework
ispTRACY™ internal logic analyzer
use
packaging
– 1 to 7.8 Mbits memory
– True Dual Port/Pseudo Dual Port/Single
– Dedicated FIFO logic for all block RAM
– 500MHz performance
– Frequency range from 15MHz to 1GHz
– Spread spectrum support
– Frequency range from 100MHz to 700MHz
– 700MHz primary and 325 MHz secondary
– 1GHz I/O-connected edge clocks
– Phase matched x2 and x4 division of incom-
– Glitch free clock MUX
– Connects to peripheral user interfaces for
Port
clocks
ing clocks
run-time dynamic configuration
Introduction
DS1004 Introduction_01.7
Data Sheet DS1004