LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 63

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Input Delay Block/AIL Timing
GSR Timing
Internal System Bus Timing
t
t
jt
1. N = number of fine delays used in a particular AIL setting
t
t
Note: Synchronous GSR goes out of reset in two cycles from the clock edge where the setup time of the FF was met.
t
Note: There is no minimum frequency. If HCLK is sourced from the embedded oscillator, the minimum frequency limitation of the oscillator/
divider is about 0.3 MHz. Refer to the osciallator data for missing configuration modes.
FDEL
CDEL
SYNC_GSR_MAX
ASYNC_GSR_MPW
HCLK
AIL
Parameter
Parameter
Parameter
Fine delay time
Coarse delay time
AIL jitter tolerance
Maximum operating frequency for 
synchronous GSR
Minimum pulse width of
asynchronous input
Maximum operating frequency for internal
system bus HCLK.
Description
Description
Description
1- ((N
1
1.14V
0.95V
* t
VCC
—
FDEL
3-19
1120
Min.
) / (Clock Period))
35
Min.
Min.
—
—
—
—
-7
-7
Max.
Max.
200
438
378
—
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
Min.
Min.
—
—
—
—
1440
-6
-6
Typ.
45
Max.
Max.
417
355
200
—
Min.
Min.
3.3
—
—
—
Max.
2560
80
-5
-5
Max.
Max.
398
337
200
—
Units
ps
ps
UI
Units
Units
MHz
MHz
MHz
ns