LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 24

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-21. Input DDR/Shift Register Block
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of registers for DDR
and shift register operation. The output signal (DO) can be derived directly from one of the inputs (bypass mode),
the SDR register or the DDR/shift register block. Figure 2-22 shows the diagram of the Output Register Block.
Output SDR Register/Latch Block
The SDR register operates on the positive edge of the high-speed clock. It has clock enable that is driven by the
clock enable output signal generated by the control MUX. In addition it has a variety of programmable options for
set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR (LSR has precedence over
CE) and Global Set Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated
from the PIO control MUX. The GSR inputs is driven from the GSR output of the PIO control MUX, which allows the
global set-reset to be disabled on a PIO basis.
Output DDR/Shift Block
The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the
high-speed clock and the associated transfer from the low-speed clock domain. It functions as a gearbox allowing
low-speed parallel data from the FPGA fabric be output as a higher speed serial stream. Each PIO supports DDR
and x2 shift functions. If desired PIOs A and B or C and D can be combined to form x4 shift functions. Figure 2-22
shows a simplified block diagram of the shift register block.
(From Delay Block)
Data Input
NEG Update
POS Update
HCLKIN
LCLKIN
From paired PIO
for wide muxing
From paired PIO
for wide muxing
for wide muxing
To paired PIO
for wide muxing
To paired PIO
2-20
Half Clock Transfer
Used for DDR with
Bypass used for DDR
Bypass used for DDR
LatticeSC/M Family Data Sheet
(Can act as INEG2
(Can act as INEG3
(Can act as IPOS2
(Can act as IPOS3
Architecture
when paired)
when paired)
when paired)
when paired)
IPOS0
IPOS1
INEG0
INEG1