LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 30

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
3. Bottom Side (Banks 4 and 5)
Table 2-8 lists the standards supported by each side.
Table 2-8. I/O Standards Supported by Different Banks
Supported Standards
The LatticeSC PURESPEED I/O buffer supports both single-ended and differential standards. Single-ended stan-
dards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVC-
MOS 12, 15, 18, 25 and 33 standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable
options for drive strength, termination resistance, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper
latch) and open drain. Other single-ended standards supported include SSTL, HSTL, GTL (input only), GTL+ (input
only), PCI33, PCIX33, PCIX15, AGP-1X33 and AGP-2X33. Differential standards supported include LVDS, RSDS,
BLVDS, MLVDS, LVPECL, differential SSTL and differential HSTL. Tables 12 and 13 show the I/O standards
(together with their supply and reference voltages) supported by the LatticeSC devices. The tables also provide the
available internal termination schemes. For further information on utilizing the PURESPEED I/O buffer to support a
variety of standards please see details of additional technical documentation at the end of this data sheet.
I/O Buffer Type
Output Standards
Supported
Input Standards 
Supported
Clock Inputs
Differential Output 
Support via Emulation
AIL Support
1. Input only.
2. Input only. Outputs supported by bussing multiple outputs together.
These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential
receivers are provided on all PIO pairs but true HLVDS and RSDS differential drivers are not available. Adap-
tive input logic is available on PIOs A or C.
Description
Single-ended, 
Differential Receiver
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18_I, II
SSTL25_ I, II
SSTL33_ I, II
HSTL15_I, II, III
HSTL18_I, II,III
SSTL18D_I, II
SSTL25D_I, II
SSTL33D_I, II
HSTL15D_I, II
HSTL18D_I, II
PCI33
PCIX15
PCIX33
AGP1X33
AGP2X33
MLVDS/BLVDS
GTL
Single-ended,
Differential
Single-ended,
Differential
LVDS/MLVDS/BLVDS/
LVPECL
No
2
, GTL+
Top Side
Banks 1
2
1
1
, IV
, IV
1
1
Single-ended, Differen-
tial Receiver and Driver
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18_I, II
SSTL25_ I, II
HSTL15_I,III
HSTL18_I,II,III
PCIX15
SSTL18D_I, II
SSTL25D_I, II
HSTL15D_I, II
HSTL18D_I, II
LVDS/RSDS
Mini-LVDS
MLVDS/BLVDS
GTL
Single-ended,
Differential
Single-ended,
Differential
MLVDS/BLVDS/
LVPECL
Yes
2
, GTL+
Right Side
Banks 2-3
2-26
2
Single-ended, 
Differential Receiver
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18_I, II
SSTL25_ I, II
SSTL33_ I, II
HSTL15_I, II, III
HSTL18_I, II,III
SSTL18D_I, II
SSTL25D_I, II
SSTL33D_I, II
HSTL15D_I, II
HSTL18D_I, II
PCI33
PCIX15
PCIX33
AGP1X33
AGP2X33
MLVDS/BLVDS
GTL
Single-ended,
Differential
Single-ended,
Differential
LVDS/MLVDS/BLVDS/
LVPECL
Yes
2
, GTL+
Bottom Side
LatticeSC/M Family Data Sheet
Banks 4-5
2
1
1
, IV
, IV
1
1
Single-ended, Differen-
tial Receiver and Driver
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18_I, II
SSTL25_ I, II
HSTL15_I,III
HSTL18_I,II,III
PCIX15
SSTL18D_I, II
SSTL25D_I, II
HSTL15D_I, II
HSTL18D_I, II
LVDS/RSDS
Mini-LVDS
MLVDS/BLVDS
GTL
Single-ended,
Differential
Single-ended,
Differential
MLVDS/BLVDS/
LVPECL
Yes
2
, GTL+
Banks 6-7
Architecture
Left Side
2