LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 77

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Descriptions (Cont.)
Lattice Semiconductor
RESETN
CFGIRQN
TSALLN
Configuration Pads (User I/O if not used. Used during sysCONFIG.)
HDC/SI
LDCN/SCS
DOUT
QOUT/CEON
RDN
WRN
CS0N CS1
A[21:0]
Signal Name
I/O
I/O
O
O
O
O
O
I
I
I
I
Reset. (Also sent to general routing). During configuration it resets the
configuration state machine. After configuration this pin can perform
the global set/reset (GSR) functions or can be used as a general input
pin.
MPI Interrupt request active low signal is controlled by system bus
interrupt controller and may be sourced from any bus error or MPI con-
figuration error. It can be connected to one of MPC860 IRQ pins.
Tristates all I/O.
High During Configuration is output high until configuration is com-
plete. It is used as a control output, indicating that configuration is not
complete.
For SPI modes, this pin is used to download the read command and
initial read address into the Flash memory device on the falling edge of
SCK. This pin will be connected to SI of the memory. If the SPI mode
is used, the 8-bit instruction code 0x03 will be downloaded followed by
a 24-bit starting address of 0x000000 or a non-zero stat address for
partial reconfiguration. If the SPIX mode has been selected, the 8-bit
instruction captured on D[7:0] at power-up will be shifted in and fol-
lowed by a 32-bit starting address of 0x000000.
Low During Configuration is output low until configuration is complete.
It is used as a control output, indicating that configuration is not com-
plete.
For SPI modes, this is an active low chip select for Flash memories. It
will go active after INITN goes high but before SCK begins. During
power up LDCN will be low. Once INITN goes high, LDCN will go high
for 100ns-200ns after which time it will go back low and configuration
can begin. During the 100ns-200ns period, the read instruction will be
latched for SPIX mode.
Serial data output that can drive the D0/DIN of daisy-chained slave
devices. The data-stream from this output will propagate preamble bits
of the bitstream to daisy-chained devices. Data out on DOUT changes
on the rising edge of CCLK.
During daisy-chaining configuration, QOUT is the serial data output
that can drive the D0/DIN of daisy-chained slave devices that do not
propagate preamble bits. Data out on QOUT changes on the rising
edge of CCLK.
During parallel-chaining configuration, active low CEON enables the
cascaded slave device to receive bitstream data.
Used in the asynchronous peripheral configuration mode. A low on
RDN changes D[7:3] into status outputs. WRN and RDN should not be
used simultaneously. If they are, the write strobe overrides.
When the FPGA is selected, a low on the write strobe, WRN, loads the
data on D[7:0] inputs into an internal data buffer.
Used in the asynchronous peripheral, slave parallel and MPI modes.
The FPGA is selected when CS0N is low and CS1 is high. During con-
figuration, a pull-up is enabled on both except with MPI DMA access
control.
In master parallel mode, A[21:0] is an output and will address the con-
figuration EPROMs up to 4 MB space. For MPI configuration mode,
A[17:0] will be the MPI address MPI_ADDR[31:14], A[19:18] will be
the transfer size and A[21:20] will be the burst mode and burst in pro-
cess.
4-3
LatticeSC/M Family Data Sheet
Description
Pinout Information