LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 17

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-13. DLL to PLL
Figure 2-14 shows a shift of only CLKOP out in time.
Figure 2-14. PLL to DLL
Figure 2-15 shows a shift of only CLKOS out in time.
Figure 2-15. PLL to DLL
For further information on the DLL, please see details of additional technical documentation at the end of this data
sheet.
sysMEM Memory Block
The sysMEM block can implement single port, true dual port, pseudo dual port or FIFO memories. Dedicated FIFO
support logic allows the LatticeSC devices to efficiently implement FIFOs without consuming LUTs or routing
resources for flag generation. Each block can be used in a variety of depths and widths as shown in Table 2-5.
Memory with ranges from x1 to x18 in all modes: single port, pseudo-dual port and FIFO also providing x36.
CLKI
CLKI
CLKI
SMI Bus
DLL
PLL
PLL
CLKOS
CLKOP
CLKOS
2-13
SMI Bus
SMI Bus
PLL
DLL
DLL
LatticeSC/M Family Data Sheet
CLKOP
CLKOS
CLKOS
CLKOS
Architecture