LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 46

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Power Supply Ramp Rates
Hot Socketing Specifications
DC Electrical Characteristics
t
1. See the Power-up and Power-Down requirements section for more details on power sequencing.
2. From 0.5V to minimum operating voltage.
Symbol
Symbol
I
1. See Hot Socket power up/down information in Chapter 2 of this document.
2. Assumes monotonic rise/fall rates for all power supplies.
3. Sensitive to power supply sequencing as described in hot socketing section.
4. Assumes power supplies are between 0 and maximum recommended operations conditions.
5. IDK is additive to I
6. Represents DC conditions. For the first 20ns after hot insertion, current specification is 8 mA.
7. Assumes that the device is powered down with all supplies grounded, both P and N inputs driven by a CML driver with maximum allowed
I
I
I
I
I
I
I
I
I
V
C1
C3
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
2. T
3. I
4. This table does not apply to SERDES pins.
5. For programmable I/Os.
RAMP
Symbol
DK
I
IL,
PU
PD
BHLS
BHHS
BHLO
BHLH
CL
CH
HDIN
BHT
VDDOB of 1.575V, 8b/10b data and internal AC coupling.
with the output driver active. Bus maintenance circuits are disabled.
2
I
PU,
A
IH
25°C, f = 1.0MHz
1
I
PD
Power supply ramp rates for all power supplies
, I
Programmable and dedicated Input or I/O leakage
current
SERDES average input current when device powered
down and inputs driven
Input or I/O Low leakage
I/O Active Pull-up Current 0  V
I/O Active Pull-down Cur-
rent
Bus Hold Low Sustaining 
Current
Bus Hold High Sustaining 
Current
Bus Hold Low Overdrive 
Current
Bus Hold High Overdrive 
Current
PCI Low Clamp Current
PCI High Clamp Current
Bus Hold trip Points
I/O Capacitance
Dedicated Input
Capacitance
BHLS
and I
2, 3, 4, 5, 6
Parameter
PU
BHHS
, I
2
PD
have minimum values of 15 or -15µA if V
or I
2
Parameter
BH
.
Parameter
7
0  V
V
V
V
0  V
0  V
-3 < V
V
0  V
V
V
V
V
V
V
Over Recommended Operating Conditions
IL
IN
IN
CC
CCIO
CC
CCAUX
CCIO
CC
CCAUX
(MAX)  V
= V
= 0.7V
+ 4 > V
= 1.2V, V
= 1.2V, V
IN
IN
IN
IN
IN
IN
= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
IL
 V
 0.7 V
 V
 V
 V
= 2.5, V
= 2.5, V
 -1
(MAX)
CCIO
5
1
IH
IH
IH
IH
IN
Condition
(MAX)
(MAX)
(MAX)
(MAX)
CCIP2
CCIP2
IN
 V
CCIO
IO
IO
 V
CC
= 0 to V
= 0 to V
= 1.2V,
= 1.2V,
IH
+ 1
Over process, voltage, 
temperature
(MAX)
3-2
CCIO
IH
IH
(MAX)
(MAX)
is set to 1.2V nominal.
0 <= V
Condition
Condition
IN
-25 + (V
<= V
25 + (V
DC and Switching Characteristics
IH
V
IL
LatticeSC/M Family Data Sheet
(MAX)
0.015
Min.
IN
IN
-30
-30
30
30
(MAX)
—
—
—
—
—
+ 1)/0.015
- V
3
CC
-1)/
Min.
Min.
3.45
—
—
—
Typ.
Typ.
—
—
—
—
—
—
—
—
—
—
Typ.
8
6
—
—
—
—
V
±1500
Max
IH
Max
Max.
-210
-210
75
—
4
210
210
10
—
—
—
—
—
—
(MIN)
mV/µs
Units
Units
mA
Units
µA
ms
mA
mA
µA
µA
µA
µA
µA
µA
µA
pf
pf
V