LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 25

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-22. Output Register Block
Figure 2-23. Output/Tristate DDR/Shift Register Block
(Can act as ONEG3
(Can act as OPOS3
(Can act as ONEG2
(Can act as OPOS2
when paired)
when paired)
when paired)
when paired)
OPOS1
ONEG0
ONEG1
OPOS0
POS Update
NEG Update
LCLKOUT
HCLKOUT
Routing
Control
From
From
MUX
HCLKOUT
LCLKOUT
OPOS0
ONEG0
OPOS1
ONEG1
Notes:
1. CE, Update, Set and Reset not shown for clarity.
2. By four shift modes utilizes DDR/Shift register block from paired PIO.
3. DDR/Shift register block shared with tristate block.
DDR/DDRX Modes
DDR/DDRX Modes
Bypass Used for
Bypass Used for
1
DDR/Shift Register Block
•
• DDR + half clock
• DDR + shift x2
• DDR + shift x4
• Shift x2
• Shift x4
DDR
2
From paired PIO
( x4 shift modes)
2
2-21
From paired PIO
( x4 shift modes)
Register
SDR
(x4 shift modes)
LatticeSC/M Family Data Sheet
To paired PIO
(x4 shift modes)
To paired PIO
Tri-state
Block
To
(to PURESPEED
I/O Buffer)
DO
Shift x2 / x4
Architecture
TSDDR/DDRX
ODDR/DDR/
Output
X2/X4