LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 67

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3-10. FIFO Reset Waveform
Note: RE and WE must be deactivated t
Figure 3-11. Read Pointer Reset Waveform
Note: RE and WE must be deactivated t
RST
EF, AE flags
FF, AF flags
DO
RE
WE
RST_B
EF, AE flags
RCLK
WE
WCLK
FF, AF flags
RE
RSU
RSU
before the Positive FIFO reset edge and enabled t
before the Positive FIFO reset edge and enabled t
t
RSF
t
t
RSU
RSU
t
RW
t
t
RSU
RSU
t
t
t
t
RSH
RSH
RSF
RSF
t
3-23
RW
t
ACCESS_F
RESET pulse width (t
RESET hold time (t
t
t
RSH
RSH
t
ACCESS_E
Asynchronous RESET, RESET pulse width (t
RESET to Flag valid (t
RSH
RW
)
), RESET to Flag valid (t
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
RSH
RSH
RSF
after the FIFO reset negative edge.
after the FIFO reset negative edge.
), RESET hold time (t
RSF
),
RW
RSH
),
)