LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 39

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
• 8-bit SERDES Only
• 10-bit SERDES Only
• SONET (STS-12/STS-48)
• Gigabit Ethernet
• Fibre Channel
• XAUI
• Serial RapidIO
• PCI-Express
• Generic 8b10b
flexiPCS Quad
The flexiPCS logic is arranged in quads containing logic for four independent full-duplex data channels. Each
device in the LatticeSC family has up to eight quads of flexiPCS logic. The LatticeSC Family Selection Guide table
on the first page of this data sheet contains the number of flexiPCS channels present on the chip. Note that in some
packages (particularly lower pin count packages), not all channels from all quads on a given device may be bonded
to package pins.
Each quad supports up to four channels of full-duplex data and can be programmed into any one of several proto-
col based modes. Each quad requires its own reference clock which can be sourced externally or from the FPGA
logic. The user can utilize between one and four channels in a quad, depending on the application.
Figure 2-30 shows an example of four flexiPCS quads in a LatticeSC device. Quads are labeled according to the
address of their software controlled registers.
Figure 2-30. LatticeSC flexiPCS
Since each quad has its own reference clock, different quads can support different standards on the same chip.
This feature makes the LatticeSC family of devices ideal for bridging between different standards.
SERDES Interface
High Speed
PCS/FPGA
Serial Data
Quad 360
Quad 360
flexiPCS
flexiPCS
Interface
SERDES Interface
High Speed
Serial Data
PCS/FPGA
Quad 361
Quad 361
Interface
flexiPCS
flexiPCS
FPGA Logic
FPGA Logic I/Os
FPGA Logic I/Os
2-35
SERDES Interface
High Speed
Serial Data
PCS/FPGA
Quad 3E1
Quad 3E1
flexiPCS
flexiPCS
Interface
LatticeSC/M Family Data Sheet
SERDES Interface
High Speed
Serial Data
PCS/FPGA
Quad 3E0
Quad 3E0
flexiPCS
flexiPCS
Interface
Architecture