LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 32

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-10. Supported Output Standards
PCI Clamp
A programmable PCI clamp is available on the top and bottom banks of the device. The PCI clamp can be turned
“ON” or “OFF” on each pin independently. The PCI clamp is used when implementing a 3.3V PCI interface. The
Single-ended Interfaces
LVTTL/D
LVCMOS33/D
LVCMOS25/D
LVCMOS18/D
LVCMOS15/D
LVCMOS12/D
PCIX15
PCI33, PCIX33, AGP1X33,
AGP2X33
HSTL18_I
HSTL18_II
HSTL15_I
HSTL15_II
SSTL33_I
SSTL33_II
SSTL25_I
SSTL25_II
SSTL18_ I
SSTL18_II
Differential Interfaces
SSTL18D_I
SSTL25D_I
SSTL18D_II, SSTL25D_II
SSTL33D_I, II
HSTL15D_I, HSTL18D_I
HST15D_II, HSTL18D_II
LVDS
Mini-LVDS
BLVDS25
MLVDS25
LVPECL33
RSDS
1. D refers to open drain capability.
2. User can select either drive current or driver impedances but not both.
3. Emulated with external resistors.
4. No GTL or GTL+ support.
Output Standard
1
3
1
1, 2
1, 2
1, 2
1, 2
4mA, 8mA, 12mA, 16mA,
4mA, 8mA, 12mA, 16mA,
4mA, 8mA, 12mA, 16mA,
2mA, 3.5mA, 4mA, 6mA
2mA, 3.5mA, 4mA, 6mA
2mA, 4mA, 8mA, 12mA
8mA, 16mA, 24mA
8mA, 16mA, 24mA
3.5mA, 4mA, 6mA
Drive
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4
2-28
V
1.2/2.5/3.3
CCIO
1.5/1.8
1.5/1.8
N/A
N/A
N/A
N/A
N/A
3.3
3.3
2.5
1.8
1.5
1.2
1.5
3.3
1.8
1.8
1.5
1.5
3.3
3.3
2.5
2.5
1.8
2.5
3.3
3.3
1.8
1.8
(Nom)
None.
None
None, series: 25, 33, 50, 100
None, series: 25, 33, 50, 100
None, series: 25, 33, 50, 100
None, series: 25, 33, 50, 100
None
None
None, series: 50
None, series: 25, series + parallel to V
2: 25 + 60
None, series: 50
None, series: 25, series + parallel to V
2: 25 + 60
None
None
None, series: 50
None, series: 33, series + parallel to V
2: 33+ 60
None, series: 33
None, series: 33, series + parallel to V
2: 33+ 60
None, series: 33
None, series: 50
None, series: 33, series + parallel to V
2: 33+ 60
None
None, series: 50
None, series: 25, series + parallel to V
2: 25 + 60
None
None
None
None
None
None
LatticeSC/M Family Data Sheet
On-chip Output Termination
Architecture
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
/
/
/
/
/
/