LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 4

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
DLLs and dynamic glitch free clock MUXs which are required in today’s high end system designs. High-speed,
high-bandwidth I/O make this family ideal for high-throughput systems.
The ispLEVER
ticeSC family of FPGA devices. Synthesis library support for LatticeSC is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeSC device. The ispLEVER tool extracts the timing from the routing and back-
annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeSC family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
Innovative high-performance FPGA architecture, high-speed SERDES with PCS support, sysMEM embedded
memory and high performance I/O are combined in the LatticeSC to provide excellent performance for today’s
leading edge systems designs. Table 1-3 details the performance of several common functions implemented within
the LatticeSC.
Table1-3. Speed Performance for Typical Functions
®
design tool from Lattice allows large complex designs to be efficiently implemented using the Lat-
32-bit Address Decoder
64-bit Address Decoder
32:1 Multiplexer
64-bit Adder (ripple)
32x8 Distributed Single Port (SP) RAM
64-bit Counter (up or down counter, non-loadable)
True Dual-Port 1024x18 bits
FIFO Port A: x36 bits, B: x9 bits
1. For additional information, see Typical Building BLock Function Performance table
2. Advance information (-7 speed grade).
in this data sheet.
Functions
1
1-3
Performance (MHz)
LatticeSC/M Family Data Sheet
539
517
779
353
768
369
372
375
2
Introduction