AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 73

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-104 • Minimum and Maximum DC Input and Output Levels
Figure 2-21 • AC Loading
Table 2-105 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-106 • SSTL 3 Class I – Applies to 1.5 V DC Core Voltage
Table 2-107 • SSTL 3 Class I – Applies to 1.2 V DC Core Voltage
SSTL3 Class I
Drive
Strength
14 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.2
*
Speed Grade
Std.
Note:
Speed Grade
Std.
Note:
Measuring point = V
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class
I. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 1.5 V
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Min.
–0.3
V
Input High (V)
VREF + 0.2
t
t
trip
DOUT
0.98
DOUT
1.55
VIL
VREF – 0.2 VREF + 0.2
. See
Max.
V
Table 2-22 on page 2-23
2.05
2.32
t
t
DP
DP
Measuring Point* (V)
0.19
0.26
t
t
DIN
DIN
Min.
Test Point
V
VIH
1.09
1.32
t
t
J
J
1.5
PY
PY
= 70°C, Worst-Case VCC = 1.425 V,
= 70°C, Worst-Case VCC = 1.14 V,
Max.
3.6
V
SSTL3
Class I
for a complete table of trip points.
t
t
0.67
1.10
25
EOUT
EOUT
R e v i s i o n 8
Max.
VOL
0.7
V
V
VREF (typ.) (V)
2.09
2.37
TT
t
t
ZL
ZL
50
30 pF
VCCI – 1.1 14 14
1.5
VOH
Min.
V
1.71
2.02
t
Table 2-6 on page 2-6
t
Table 2-7 on page 2-6
ZH
ZH
mA mA
I
t
t
OL
LZ
LZ
VTT (typ.) (V)
I
OH
t
t
IGLOOe Low Power Flash FPGAs
HZ
HZ
1.485
Max.
I
mA
OSH
51
5.72
8.17
t
t
ZLS
ZLS
3
for derating values.
for derating values.
Max.
mA
I
OSL
t
5.34
t
7.83
54
ZHS
ZHS
C
3
LOAD
30
µA
I
10 10
IL
Units
Units
(pF)
1
4
ns
ns
µA
I
2- 59
IH
2
4