AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 18
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AGLE600V2-FGG484
Manufacturer Part Number
AGLE600V2-FGG484
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AGLE600V2-FGG484.pdf
(158 pages)
Specifications of AGLE600V2-FGG484
Processor Series
AGLE600
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
270
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGLE600V2-FGG484
Manufacturer:
Actel
Quantity:
135
Company:
Part Number:
AGLE600V2-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
IGLOOe DC and Switching Characteristics
Figure 2-1 • V5 – I/O State as a Function of VCCI and VCC Voltage Levels
2 - 4
Deactivation trip point:
V
V
Activation trip point:
a
d
= 0.85 V ± 0.25 V
= 0.75 V ± 0.25 V
VCC = 1.575 V
VCC = 1.425 V
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup
behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see
2 on page 2-5
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±
0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the
"Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the
Guide
Internal Power-Up Activation Sequence
Output buffers, after 200 ns delay from input buffer activation.
VCC
•
1. Core
2. Input buffers
for information on clock and lock recovery.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Region 1: I/O Buffers are OFF
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
for more details).
Deactivation trip point:
Activation trip point:
V
V
a
d
= 0.9 V ± 0.3 V
= 0.8 V ± 0.3 V
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
buffers do not meet VOH / VOL levels.
meet VIH / VIL levels, and output
same reason, input buffers do not
is below specification. For the
but slower because VCCI
(except differential
(except differential inputs)
I/Os are functional
I/Os are functional
R e vi s i o n 8
buffers are ON.
buffers are ON.
Region 4: I/O
Region 4: I/O
Min VCCI datasheet specification
standard; i.e., 1.425 V or 1.7 V
voltage at a selected I/O
or 2.3 V or 3.0 V
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
IGLOOe FPGA Fabric User’s
Figure 2-1
and
VCCI
Figure 2-