AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 154

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4 - 4
Revision
Revision 2 (cont’d)
Packaging v1.1
Revision 1 (Mar 2008)
Product Brief rev. 1
Revision 0 (Jan 2008) This document was previously in datasheet Advance v0.4. As a result of moving
Advance v0.4
(December 2007)
The naming conventions changed for the following pins in the
the A3GLE600:
Pin Number
J19
K20
M2
N1
N4
P3
The
to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 25 µW)" was removed
from "Low Power Active FPGA Operation."
1.2_V was added to the list of core and I/O voltages in the
and
to the handbook format, Actel has restarted the version numbers. The new
version number is 51700096-001-0.
The
number of user I/Os for AGLE3000.
The
dimensions were removed from the "I/Os Per Package1" table. The number of
I/Os was updated for FG896.
A note regarding marking information was added to the
Information"
Table 2-4 • IGLOOe CCC/PLL Specification and Table 2-5 • IGLOOe CCC/PLL
Specification were updated.
The "During Flash*Freeze Mode" section was updated to include information
about the output of the I/O to the FPGA core
Figure 2-38 • Flash*Freeze Mode Type 1 – Timing Diagram was updated to
modify the LSICC signal.
Table 2-32 • Flash*Freeze Pin Location in IGLOOe Family Packages (device-
independent) was updated for the FG896 package.
Figure 2-40 • Flash*Freeze Mode Type 2 – Timing Diagram was updated to
modify the LSICC Signal.
Information regarding calculation of the quiescent supply current was added to
the "Quiescent Supply Current" section.
Table 3-8 • Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode† was
updated.
Table 3-9 • Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)†
was updated.
Table 3-11 • Quiescent Supply Current, No IGLOOe Flash*Freeze Mode1 was
updated.
"Pro I/Os with Advanced I/O Standards" section
Table 1 • IGLOOe Product Family
"Low Power" section
"IGLOOe FPGAs Package Sizes Dimensions" table
table.
New Function Name
IO45PPB2V1
IO45NPB2V1
IO114NPB6V1
IO114PPB6V1
GFC2/IO115PPB6V1
IO115NPB6V1
was updated to change "1.2 V and 1.5 V Core Voltage"
R e vi s i o n 8
Changes
table was updated to change the maximum
.
sections.
"Pro (Professional) I/O"
table is new. Package
"484-Pin FBGA"
"IGLOOe Ordering
for
Page
I,
2-18,
2-19
2-60
2-56
2-64
2-58
N/A
3-6
3-6
3-6
3-6
3-6
III
1-7
II
I
I