AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 153

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
Revision 3 (cont’d)
Revision 2 (Jun 2008)
Product Brief v1.0
The table notes for
Flash*Freeze
Mode (VCC = 0
Shutdown Mode (VCC, VCCI = 0 V)*
P
the table note for
Shutdown Mode (VCC, VCCI = 0
Note 2 of
Mode*
P
Table note 3 was added to
pin) – Default I/O Software Settings
Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings
reflect that power was measured on V
Table 2-15 • Different Components Contributing to the Static Power Consumption
in IGLOO Devices
Static Power Consumption in IGLOO Devices
P
A table subtitle was added for
the Static Power Consumption in IGLOO
The
calculation of P
Footnote 1
Contribution equation was changed from: P
PPLL = P
The
numbers.
In
changed to T
Table 2-21 • Summary of Maximum and Minimum DC Input Levels
to included a hysteresis value for 1.2 V LVCMOS (Schmitt trigger mode).
All AC Loading figures for single-ended I/O standards were changed from
Datapaths at 35 pF to 5 pF.
The
The product brief section of the datasheet was divided into two sections and
given a version number, starting at v1.0. The first section of the document
includes features, benefits, ordering information, and temperature and speed
grade offerings. The second section is a device family overview.
DC6
DC7
DC7
Table 2-21 • Summary of Maximum and Minimum DC Input
"Total Static Power Consumption—P
"1.2 V LVCMOS (JESD8-12A)" section
.
, and to change the definition for P
"Timing Model"
and P
was updated to include V
1
DC4
was updated to change P
Table 2-11 • Quiescent Supply Current, No IGLOOe Flash*Freeze
DC7
was updated to include information about P
A
+ P
Mode*,
in notes 1 and 2.
STAT
. V
V)*, and
AC13
CCI
, including P
and
Table 2-10 • Quiescent Supply Current (IDD), IGLOOe
Table 2-9 • Quiescent Supply Current (I
* F
and V
was updated to be consistent with the revised timing
Table 2-8 • Quiescent Supply Current (I
Table 2-17 • Different Components Contributing to the
CLKOUT.
Table 2-10 • Quiescent Supply Current (IDD), IGLOOe
Table 2-12 • Summary of I/O Input Buffer Power (per
JTAG
Table 2-17 • Different Components Contributing to
DC6
CCPLL
V)*.
were removed from the statement about I
R e v i s i o n 8
DC3
Changes
and referenced for 1.2 V LVCMOS.
and P
CCI.
were updated to remove VMV and include
. Note 4 was updated to include P
to P
DC5
Devices.
STAT
DC7
Table note 4 is new.
DC7
to bank quiescent power.
is new.
PLL
.
" section
. The table notes were updated to
were updated to add P
= P
AC13
was updated to revise the
+ P
AC14
DD
IGLOOe Low Power Flash FPGAs
), IGLOOe Sleep
AC13
Levels, T
* FCLKOUT to
DD
was updated
. The PLL
), IGLOOe
DC6
DC6
J
DD
was
and
and
in
2-11,
Page
2-10
2-12
2-13
2-14
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2-22
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