AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 71

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-96 • Minimum and Maximum DC Input and Output Levels
Figure 2-19 • AC Loading
Table 2-97 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-98 • SSTL 2 Class I – Applies to 1.5 V DC Core Voltage
Table 2-99 • SSTL 2 Class I – Applies to 1.2 V DC Core Voltage
SSTL2
Class I
Drive
Strength
15 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.2
*
Speed Grade
Std.
Note:
Speed Grade
Std.
Note:
Measuring point = V
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Min.
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class
I. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
–0.3 VREF – 0.2 VREF + 0.2
Commercial-Case Conditions: T
Worst-Case VCCI = 2.3 V VREF = 1.25 V
Commercial-Case Conditions: T
Worst-Case VCCI = 2.3 V VREF = 1.25 V
V
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Input High (V)
VIL
VREF + 0.2
t
t
trip
DOUT
0.98
DOUT
1.55
Max.
V
. See
Table 2-22 on page 2-23
1.91
2.17
t
t
DP
DP
Min.
Measuring Point* (V)
V
0.19
0.26
t
t
DIN
DIN
VIH
Test Point
1.25
1.15
1.39
Max.
t
t
J
J
3.6
PY
PY
V
= 70°C, Worst-Case VCC = 1.425 V,
= 70°C, Worst-Case VCC = 1.14 V,
SSTL2
Class I
for a complete table of trip points.
t
t
Max.
0.67
1.10
VOL
25
EOUT
EOUT
0.54
R e v i s i o n 8
V
VREF (typ.) (V)
V
VCCI – 0.62 15 15
1.94
2.21
TT
t
t
ZL
ZL
50
VOH
Min.
30 pF
1.25
V
1.72
2.04
t
Table 2-6 on page 2-6
t
Table 2-7 on page 2-6
ZH
ZH
mA mA
I
OL
t
t
LZ
LZ
I
VTT (typ.) (V)
OH
t
t
IGLOOe Low Power Flash FPGAs
1.25
HZ
HZ
Max.
mA
I
OSH
83
3
5.57
8.02
t
t
ZLS
ZLS
for derating values.
for derating values.
Max.
mA
I
OSL
87
t
5.35
t
7.84
C
ZHS
ZHS
3
LOAD
30
µA
I
IL
10 10
(pF)
Units
Units
1
4
ns
ns
µA
I
2- 57
IH
2
4