AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 151

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AGLE600V2-FGG484

Manufacturer Part Number
AGLE600V2-FGG484
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGLE600V2-FGG484

Processor Series
AGLE600
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
270
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGLE600V2-FGG484
Manufacturer:
Actel
Quantity:
135
Part Number:
AGLE600V2-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
4 – Datasheet Information
List of Changes
Revision
July 2010
Revision 8 (Nov 2009) The version changed to v2.0 for IGLOOe datasheet chapters, indicating the
Product Brief v2.0
DC
Characteristics v2.0
and
Switching
The following table lists critical changes that were made in each revision of the IGLOOe datasheet.
The versioning system for datasheets has been changed. Datasheets are
assigned a revision number that increments each time the datasheet is revised.
The
in the device family.
datasheet contains information based on final characterization.
The
sparing I/Os."
The
(1.5 V systems) and 160 MHz (1.2 V systems) System Performance."
Definitions of hot-swap and cold-sparing were added to the
Advanced I/O Standards"
3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the
datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V
LVCMOS data.
I
Maximum DC Input and Output Levels" tables.
Values for 1.2 V wide range DC core supply voltage were added to
Recommended Operating Conditions
and the core voltage required for programming were added to the table.
The data in
Delays
Derating Factors for Timing Delays
3.3 V LVCMOS wide range data was included in
Input Buffer Power (per pin) – Default I/O Software Settings
Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
Table notes were added in connection with this data.
The temperature was revised from 110ºC to 100ºC in
Short Circuit Event before Failure
and Related I/O
The tables in the
Characteristics"
LVCMOS wide range.
Most tables were updated in the following sections, revising existing values and
adding information for 3.3 V and 1.2 V wide range:
"Single-Ended I/O Characteristics"
"Voltage-Referenced I/O Characteristics"
"Differential I/O Characteristics"
IL
and I
"Pro (Professional) I/O" section
"IGLOOe Device Status" table on page II
"Reprogrammable Flash Technology" section
(1.5 V DC core supply voltage) and
IH
input leakage current information was added to all "Minimum and
Table 2-6 • Temperature and Voltage Derating Factors for Timing
Reliability*.
sectionwere revised to include 3.3 V LVCMOS and 1.2 V
"Overview of I/O Performance" section
section.
R e v i s i o n 8
and
(1.2 V DC core supply voltage) was revised.
Changes
was revised to add "Hot-swappable and cold-
1
Table 2-32 • I/O Input Rise Time, Fall Time,
. Table notes regarding 3.3 V wide range
Table 2-7 • Temperature and Voltage
indicates the status for each device
was revised to add "250 MHz
Table 2-12 • Summary of I/O
Table 2-30 • Duration of
and
and
"Detailed I/O DC
"Pro I/Os with
Table 2-13 •
Table 2-2 •
1
.
2-30,
2-20,
2-50,
2-9,
Page
2-31,
N/A
N/A
N/A
N/A
1-7
2-2
2-6
I
I
2-10
2-30
2-27
2-61
4 -1

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