AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 105

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-143 • IGLOOe CCC/PLL Specification
Note:
Figure 2-40 • Peak-to-Peak Jitter Definition
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Serial Clock (SCLK) for Dynamic PLL
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay
Block
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. Maximum value obtained for a Std. speed grade device in Worst Case Commercial Conditions. For specific junction
2. This delay is a function of voltage and temperature. See
3. T
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
temperature and voltage supply levels, refer to
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
J
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 160 MHz
= 25°C, V
Peak-to-peak jitter measurements are defined by T
Output Signal
For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage
CC
= 1.5 V
2, 3
1
CCC_OUT
IN_CCC
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
2, 3
2, 3
OUT_CCC
Table 2-6 on page 2-6
2, 3
T
period_max
peak-to-peak
Table 2-6 on page 2-6
R e v i s i o n 8
= T
for derating values.
1 Global
Network
0.50%
1.00%
2.50%
period_max
0.863
Used
Min.
0.75
48.5
T
2.3
1.5
period_min
Max Peak-to-Peak Period Jitter
and
– T
Table 2-7 on page 2-6
FB Used
External
0.75%
1.50%
3.75%
period_min
Typ.
580
5.7
IGLOOe Low Power Flash FPGAs
.
Networks
3 Global
0.70%
1.20%
2.75%
20.86
20.86
Used
Max.
0.25
160
160
300
51.5
6.0
60
32
4
3
for deratings.
Units
MHz
MHz
MHz
ms
ps
ns
µs
ns
ns
ns
ns
ns
%
2- 91