AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 39

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
3.3 V LVCMOS
Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
LVPECL
Notes:
1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b
2. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at
3. Resistance is used to measure I/O propagation delays as defined in PCI Specifications.
4. For specific junction temperature and voltage supply levels, refer to
specification.Resistance is used to measure I/O propagation delays as defined in PCI specifications. See
page 2-48
the equivalent software default drive strength. These values are for normal ranges
1, 2
for connectivity. This resistor is not required during normal operation.
Std. Speed Grade, Commercial-Case Conditions: T
Worst-Case VCCI (per standard)
100 µA
PCI-X
spec
spec
PCI
Per
Per
12
21
12
12
12
25
25
35
33
15
15
18
14
24
24
8
12
12
12
12
12
–
–
–
–
–
–
–
–
–
–
–
–
–
–
High
High
High 30
High 30
High 30
High
High
High
High 10 25
High 10 25
High 10
High 10
High 10
High 10
High 20
High 20
High 30
High
High
5
5
5
5
5
–
–
25 0.97 1.78 0.19 2.35
25 0.97 1.85 0.19 1.98
25 0.97 1.80 0.19 1.32
25 0.97 1.92 0.19 1.26
50 0.97 2.67 0.18 1.72
25 0.97 2.55 0.18 1.72
50 0.97 1.86 0.19 1.12
25 0.97 1.89 0.19 1.12
50 0.97 2.00 0.19 1.06
25 0.97 1.81 0.19 1.06
–
–
–
–
–
– 0.97 1.73 0.19 1.62
– 0.97 1.65 0.18 1.42
3
3
0.97 2.12 0.18 1.08 1.34 0.66 2.17 1.69 2.71 3.08 5.76 5.28 ns
0.97 2.96 0.18 1.42 1.84 0.66 2.98 2.28 3.86 4.36 6.58 5.87 ns
.097 2.15 0.18 1.31 1.41 0.66 2.20 1.85 2.78 2.98 5.80 5.45 ns
0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns
0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns
0.97 2.38 0.18 0.96 1.42 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns
0.97 2.38 0.19 0.92 1.34 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns
R e v i s i o n 8
Table 2-6 on page 2-6
J
= 70°C, Worst-Case VCC = 1.425 V,
–
–
–
–
–
–
–
–
–
–
–
–
0.66 1.80 1.78
0.66 1.89 1.82
0.66 1.84 1.77
0.66 1.96 1.80
0.66 2.72 2.67
0.66 2.60 2.34
0.66 1.90 1.68
0.66 1.93 1.62
0.66 2.04 1.67
0.66 1.85 1.55
–
–
–
–
IGLOOe Low Power Flash FPGAs
–
–
for derating values.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5.39 5.38 ns
5.49 5.42 ns
5.44 5.36 ns
5.56 5.40 ns
6.32 6.26 ns
6.20 5.93 ns
5.50 5.28 ns
5.53 5.22 ns
5.64 5.27 ns
5.45 5.14 ns
Figure 2-12 on
–
–
–
–
2- 25
ns
ns