AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 57

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-57 • Minimum and Maximum DC Input and Output Levels
Figure 2-10 • AC Loading
Table 2-58 • AC Waveforms, Measuring Points, and Capacitive Loads
1.5 V
LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
*
Measuring point = V
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
V
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Test Point
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
Datapath
VIL
Max.
trip
V
Input High (V)
. See
1.5
Table 2-22 on page 2-23
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
35 pF
Min.
V
VIH
Measuring Point* (V)
Enable Path
Max.
Test Point
3.6
3.6
3.6
3.6
3.6
V
R = 1 k
0.75
0.25 * VCCI
0.25 * VCCI
0.25 * VCCI
0.25 * VCCI
0.25 * VCCI
for a complete table of trip points.
R e v i s i o n 8
Max.
VOL
V
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
0.75 * VCCI
0.75 * VCCI
0.75 * VCCI
0.75 * VCCI
0.75 * VCCI
VOH
Min.
V
V
REF
HZ
ZH
(typ.) (V)
/ t
–
/ t
LZ
HZ
LZ
ZHS
mA mA
I
12 12
OL
2
4
6
8
/ t
/ t
IGLOOe Low Power Flash FPGAs
ZL
ZH
I
/ t
OH
2
4
6
8
ZL
/ t
/ t
ZLS
ZHS
/ t
Max.
mA
I
OSH
13
25
32
66
66
ZLS
3
C
LOAD
Max.
mA
I
OSL
16
33
39
55
55
5
3
(pF)
µA
I
IL
10 10
10 10
10 10
10 10
10 10
1
4
µA
2- 43
I
IH
2
4