AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 11

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1-2 • IGLOOe Flash*Freeze Mode
X1
X2
X3
Figure 1-3 • VersaTile Configurations
LUT-3 Equivalent
LUT-3
static and dynamic capabilities of the IGLOOe device. Refer to
entering/exiting Flash*Freeze mode.
VersaTiles
The IGLOOe core consists of VersaTiles, which have been enhanced beyond the ProASIC
tiles. The IGLOOe VersaTile supports the following:
Refer to
User Nonvolatile FlashROM
Actel IGLOOe devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM
can be used in diverse system applications:
The FlashROM is written using the standard IGLOOe IEEE 1532 JTAG programming interface. The core
can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks, as in security keys stored in the FlashROM for a
user design.
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Y
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
Figure 1-3
Mode Control
Flash*Freeze
for VersaTile configurations.
D-Flip-Flop with Clear or Set
Data
CLK
CLR
D-FF
R e v i s i o n 8
Y
Flash*Freeze Pin
Actel IGLOOe
FPGA
Enable D-Flip-Flop with Clear or Set
Enable
Data
CLK
CLR
IGLOOe Low Power Flash FPGAs
Figure 1-2
D-FF
for an illustration of
Y
PLUS®
core
1 -5