AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 67

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-80 • Minimum and Maximum DC Input and Output Levels
Figure 2-15 • AC Loading
Table 2-81 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-82 • 3.3 V GTL+ – Applies to 1.5 V DC Core Voltage
Table 2-83 • 3.3 V GTL+ – Applies to 1.2 V DC Core Voltage
3.3 V GTL+
Drive
Strength
35 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.1
*
Speed Grade
Std.
Note:
Speed Grade
Std.
Note:
Measuring point = V
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < V
is the input leakage current per I/O pin over recommended operating conditions V
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The V
Timing Characteristics
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 1.0 V
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 1.0 V
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Min.
–0.3
V
Input High (V)
t
t
VREF + 0.1
trip
DOUT
0.98
DOUT
1.55
VIL
VREF – 0.1 VREF + 0.1
. See
Max.
V
Table 2-22 on page 2-23
1.85
2.11
t
t
DP
DP
Measuring Point* (V)
0.19
0.26
t
t
DIN
DIN
Min.
V
Test Point
VIH
1.35
1.61
t
t
J
J
PY
PY
1.0
= 70°C, Worst-Case VCC = 1.425 V,
= 70°C, Worst-Case VCC = 1.14 V,
Max.
3.6
GTL+
V
for a complete table of trip points.
t
t
0.67
1.10
EOUT
EOUT
R e v i s i o n 8
V
Max.
VOL
0.6
TT
V
25
VREF (typ.) (V)
1.88
2.15
10 pF
t
t
ZL
ZL
VOH
Min.
1.0
V
–
CCI
1.81
2.07
t
Table 2-6 on page 2-6
t
Table 2-7 on page 2-6
ZH
ZH
pin should be connected to 3.3 V
mA mA
I
35 35
OL
t
t
LZ
LZ
I
OH
VTT (typ.) (V)
IH
t
t
IGLOOe Low Power Flash FPGAs
HZ
HZ
< V
Max.
I
mA
1.5
268
OSH
IN
3
5.51
7.95
t
t
< V
ZLS
ZLS
for derating values.
for derating values.
IN
CCI
Max.
mA
I
181
< V
OSL
. Input current is
t
5.44
t
7.88
ZHS
ZHS
C
3
IL
LOAD
.
10
µA
I
IL
10 10
Units
Units
(pF)
1
4
ns
ns
µA
I
2- 53
IH
2
4