XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 7

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
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E3 TRANSMIT FRAMER
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Synchronizes to incoming frame based upon occurrence of two sets of FA1, FA2 with expected separation -
G.832 or detection of three consecutive frame alignment signals (FAS) - G.751
Detects Out of Frame (OOF) upon 4 consecutive invalid frames
Detects Loss of Signal (LOS) upon encountering 32 consecutive 0’s and clears on occurrence of 32 bits
without a string of 4 0s
Detects AIS if 7 or less 0s detected in each of 2 consecutive frames and clears if more than seven 0’s
detected in each of 2 consecutive frames
Calculation and comparison of BIP-8 (G.832) or BIP-4 (G.751). BIP-4 calculation can be disabled
Supports overhead extraction
Microprocessor access to TR trail trace message - 16 TTB registers (G.832) or service (Alarm and Nation)
bits (G.751)
Detects MA FERF if 3 or 5 consecutive MA MSBs are 1and clears if 3 or 5 consecutive MA MSBs are 0 (only
E3 G.832)
Indicates last validated FERF value and interrupt upon a change in validated FERF value
Extracts payload type (MA) bits and stores in a register (Only E3 G.832)
Extracts Timing Marker bit and checks for consistency over 3 or 5 consecutive frames (only E3 G.832)
Extracts Synchronous Status Message bits and stores it in register bits when enabled (only G.832)
Overhead output on synchronous serial interface
Offers following frame generation mechanism: Asynchronous operation, using receive side clock, external
framing
Supports either G.751 or G.832 framing format
Generates and checks parity BIP-8 (G.832), BIP-4 (G.751) BIP-4 computation can be disabled
Inserts data link message through E3 data line channel which contains the following features:
LOS insertion enabled by register bit to force all 0s in the transmit stream
AIS insertion enabled by register bit and/or pin to force all 1’s in the transmit stream
Supports HDB3 encoding enabled by register bit
Inserts frame overhead bits via External serial/nibble port (except for FA1,FA2 and EM bytes in case of E3
G.832 and FAS and BIP-4 in case of G.751) or through external overhead interface or from configuration
register or internal generation
Inserts FA1, FA2, EM, TR, MA and GC bytes into G.832 stream or FAS service bits and BIP4 (if enabled) into
G.751 stream
Insertion into NR or GC byte (programmable through register bit) (E3 G.832 only)
Insertion into Nation bit in case of E3 G.751 when LAPD is enabled
RAM storage of entire LAPD message
Selection of message length to 82 or 76 bytes
Generation of flag sequences
Computation and insertion of CRC-16
Zero stuffing
Register bits for communication with microprocessors
Interrupt generation upon complete transmission of message
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