XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 35

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SONET/SDH OVERHEAD INTERFACE - TRANSMIT DIRECTION
XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
AD12
AD13
AE17
AB12
AE11
P
AD8
C10
D18
AE8
D13
C18
C13
AF4
B13
A16
D9
IN
#
TxPOH_0
TxPOH_1
TxPOH_2
TxPOH_3
TxPOH_4
TxPOH_5
TxPOH_6
TxPOH_7
TxPOH_8
TxPOH_9
TxPOH_10
TxPOH_11
TxPOH_12
TxPOH_13
TxPOH_14
TxPOH_15
S
IGNAL
N
AME
I/O
I
S
T
IGNAL
TTL
YPE
Transmit Path Overhead Input Port - Input Pin.
These input pins allow the following actions.
1. Insertion oft the POH data into each of the 12 Transmit SONET POH
Processor blocks (for insertion and transmission via the outbound STS-
12 signal.
2. Insertion of the POH data into each of the 12 Transmit STS-1 POH
Processor blocks (for insertion and transmission via each of the out-
bound STS-1 signals).
3. Insertion of the TOH data into each of the 12 Transmit STS-1 TOH
Processor blocks (for insertion and transmission via each of the out-
bound STS-1 signals).
The function of these input pins, depends upon whether or not the TOH
data is inserted into the 12 Transmit STS-1 TOH Processor blocks.
If the user is only inserting POH data via these input pins:
In this mode, the external circuitry (which is being interfaced to the
Transmit Path Overhead Input Port is suppose to monitor the following
output pins.
•
•
•
The TxPOHFrame_n output pin will toggle "High" upon the falling edge
of TxPOHClk_n approximately one TxPOHClk_n period prior to the
TxPOH port being ready to accept and process the first bit within the J1
byte (e.g., the first POH byte). The TxPOHFrame_n output pin will
remain "High" for eight consecutive TxPOHClk_n periods. The external
circuitry should use this pin to note STS-1 SPE frame boundaries.
The TxPOHEnable_n output pin will toggle "High" upon the falling edge
of TxPOHClk_n approximately one TxPOHClk_n period prior to the
TxPOH port being ready to accept and process the first bit within a given
POH byte.
To externally insert a given POH byte, (1) assert the TxPOHIns_n input
pin by toggling it "High" and (2) place the value of the first bit (within this
particular POH byte) on this input pin upon the very next falling edge of
TxPOHClk_n. This data bit will be sampled upon the very next rising
edge of TxPOHClk_n. The external circuitry should continue to keep the
TxPOHIns_n input pin "High" and advancing the next bits (within the
POH bytes) upon each falling edge of TxPOHClk_n.
If the user is inserting both POH and TOH data via these input pins:
In this mode, the external circuitry (which is being interfaced to the
Transmit Path Overhead Input Port is suppose to monitor the following
output pins.
•
•
•
(continued below)
TxPOHFrame_n
TxPOHEnable_n
TxPOHClk_n
TxPOHFrame_n
TxPOHEnable_n
TxPOHClk_n
29
D
ESCRIPTION
REV. 1.0.2