XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 184

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
P
G23
IN
#
STS3TxA_DP_1
TxDS3FP_5
TxSTS1PL_5
S
IGNAL
N
AME
I/O
I/O
S
CMOS
T
TTL/
IGNAL
YPE
STS-3/STM-1 Transmit Telecom Bus - Parity Input Pin - Channel
1, DS3/E3 Frame Generator Framing Pulse Input/Output Pin -
Channel 5:
If STS-3/STM-1 Telecom Bus (Channel 1) has been enabled -
STS-3/STM-1 Transmit Telecom Bus - Parity Input Pin:
This input pin can be configured to function as one of the following.
1. The EVEN or ODD parity value of the bits which are input via the
ST3TXA_D_1[7:0] input pins.
2. The EVEN or ODD parity value of the bits which are being input
via the STS3TXA_D_1[7:0] input and the states of the
STS3TXA_PL_1 and STS3TXA_C1J1_1 input pins.
N
If STS-3/STM-1 Telecom Bus (Channel 1) is disabled -
TxDS3FP_5 (Transmit DS3 Frame Pulse Input/Output - Channel
5):
If the STS-3/STM-1 Telecom Bus (Channel 1) is disabled and if the
DS3/E3 Framer block is enabled then this pin will function as either a
Transmit Framing Reference input pin or as a Transmit Framing Ref-
erence output pin.
If the Frame Generator (within the DS3/E3 Framer block) is con-
figured to operate in the Loop-Timing or in the Local-Timing/
Asynchronous Framing Mode:
This pin will function as a Framing Reference Output pin. The Frame
Generator block (associated with Channel 5) will pulse this output pin
"High" for one DS3/E3 bit-period, one period prior to the first bit of a
given DS3 or E3 frame being applied to the DS3/E3/
STS1_DATA_IN_5 input pin.
If the Frame Generator (within the DS3/E3 Framer block) is con-
figured to operate in the Local-Timing/TxDS3FP Mode:
This pin will function as a Framing Reference Input pin. In this mode,
the user is expected to pulse this input pin "High" for one DS3 or E3
bit-period, coincident with the first bit of a given DS3 or E3 frame,
being placed on the DS3/E3/STS1_DATA_IN_5 input pin. The Frame
Generator block (associated with Channel 5) will synchronize its gen-
eration of DS3 or E3 frames to these framing pulses applied to this
input pin.
N
OTE
OTE
: Any one of these configuration selections can be made by
: This pin is inactive if the Frame Generator block, associated
178
writing the appropriate value into the Interface Control
Register - Byte 1 register (Indirect Address = 0x00, 0x3A),
(Direct Address = 0x013A).
with Channel 5 is by-passed.
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
D
ESCRIPTION
XRT94L43