XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 134

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RECEIVE TRANSPORT OVERHEAD INTERFACE
REV. 1.0.2
P
W5
W6
W2
Y5
V6
IN
#
RxTOHClk
RxTOHValid
RxTOH
RxTOHFrame
RxLDCCVAL
S
IGNAL
N
AME
I/O
O
O
O
O
O
S
CMOS Receive TOH Output Port - Clock Output:
CMOS Receive TOH Output Port - TOH Valid (or READY) indicator:
CMOS Receive TOH Output port - Output Pin:
CMOS Receive TOH Output Port - STS-12/STM-4 Frame Indicator:
CMOS Receive - Line DCC Output Port - DCC Value Indicator Output Pin:
T
IGNAL
YPE
This output pin, along with RxTOH, RxTOHValid and RxTOHFrame func-
tion as the Receive TOH Output Port:
The Receive TOH Output Port is used to obtain the value of the TOH
Bytes, within the incoming STS-12/STM-4 signal.
This output pin provides a clock signal.
If the RxTOHValid output pin is "High", then the contents of the TOH bytes
within the incoming STS-12 data-stream, will be serially output via the
RxTOH output. This data will be updated upon the falling edge of this clock
signal. Therefore, it is advisable to sample the data (at the RxTOH output
pin) upon the rising edge of this clock output signal.
This output pin, along with RxTOH and RxTOHFrame function as the
Receive TOH Output Port.
This output pin will toggle "High" whenever valid TOH data is being output
via the RxTOH output pin.
This output pin, along with RxTOHClk, RxTOHValid and RxTOHFrame
function as the Receive TOH Output port.
All TOH data, that resides within the incoming STS-12 data-stream will be
output via this output pin.
The RxTOHValid output pin will toggle "High", coincident with anytime a bit
(from the Receive STS-12 TOH data) is being output via this output pin.
The RxTOHFrame output pin will pulse "High" (for eight periods of RxTO-
HClk) coincident to when the A1 byte is being output via this output pin.
Data, on this output pin, is updated upon the falling edge of RxTOHClk.
This output pin, along with the RxTOHClk, RxTOHValid and RxTOH output
pins function as the Receive TOH Output port.
This output pin will pulse "High", for one period of RxTOHClk, one RxTO-
HClk period prior to the very first TOH bit (of a given STS-12 frame) being
output via the RxTOH output pin.
This output pin, along with the RxTOHClk and the RxLDCC output pins
function as the Receive Line DCC output port of the XRT94L43.
This output pin pulses "High" coincident to when the Receive Line DCC
output port outputs a DCC bit via the RxLDCC output pin.
This output pin is updated upon the falling edge of RxTOHClk.
The Line DCC HDLC Controller circuitry that is interfaced to this output
pin, the RxLDCC and the RxTOHClk pins is suppose to do the following.
1. It should continuously sample and monitor the state of this output pin
upon the rising edge of RxTOHClk.
2. Anytime the Line DCC HDLC circuitry samples this output pin being
"High", it should sample and latch the data on the RxLDCC output pin (as
a valid Line DCC bit) into the Line DCC HDLC circuitry.
128
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
D
ESCRIPTION
XRT94L43