XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 44

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
AF24
P
IN
#
STS3TxA_C1J1_2
ING_LCV_IN_10
ING_RxNEG_IN_10
TxSTS1PL_10
TxSBFrame_2
S
IGNAL
N
AME
I/O
I/O
S
CMOS
T
TTL/
IGNAL
YPE
Transmit STS-3/STM-1 Telecom Bus Interface - C1/J1 Byte
Phase Indicator Input Signal (Channel 2); DS3/E3 Framer Block
LCV/RxNEG Input pin - Channel 10:
The function of this pin depends upon whether or not theSTS-3/STM-
1 Telecom Bus Interface for Channel 2 has been enabled.
If STS-3/STM-1 Telecom Bus (Channel 2) has been enabled -
STS-3/STM-1 Transmit Telecom Bus C1/J1 Byte Phase Indicator
Input Signal (Channel 2):
This input pin should be pulsed "High" during both of the following
conditions.
If STS-3/STM-1 Telecom Bus (Channel 2) is disabled - DS3/E3
Framer Block LCV/RxNEG Input - Channel 10):
If the STS-3/STM-1 Telecom Bus (Channel 2) is disabled and if the
DS3/E3 Framer block is enabled then this pin will function as either
an LCV or an RxNEG input pin.
If Channel 10 is configured to operate in the Single- Rail Mode,
and if the Primary Frame Synchronizer block is configured to
operate in the Ingress Path - ING_LCV_IN_10 Input pin:
If the Primary Frame Synchronizer Block (associated with Channel
10) is configured to operate in the Ingress Path, and if Channel 10 is
configured to operate in the Single-Rail Mode, then this input pin will
function as the "LCV" (Line Code Violation) input pin. In this case,
the user should connect this particular input pin to the "LCV" output
pin of the corresponding DS3/E3/STS-1 LIU Channel.
and if the Primary Frame Synchronizer block is configured to
operate in the Ingress Path - ING_RxNEG_IN_10:
If the Primary Frame Synchronizer block (associated with Channel
10) is configured to operate in the Ingress Path, and if Channel 10 is
configured to operate in the Dual-Rail Mode, then this input pin will
function as the "RxNEG" (Negative Polarity Data) input pin. In this
case, the user should connect this particular input to the "RxNEG"
output pin of the corresponding DS3/E3/STS-1 LIU Channel.
N
If Channel 10 is configured to operate in the Dual-Rail Mode,
OTE
1. Whenever the C1 byte is being input to the STS-3/STM-1
2. Whenever the J1 byte is being input to the STS-3/STM-1
: This pin is inactive if the Primary Frame Synchronizer block
Transmit Telecom Bus (TXA_D_2[7:0]) input pins.
Transmit Telecom Bus (TXA_D_2[7:0]) input pins.
38
(associated with Channel 10) is NOT configured to operate
in the Ingress Path.
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
D
ESCRIPTION
XRT94L43