XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 49

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
AE19
P
IN
#
STS3TxA_DP_3
ING_LCV_IN_7
ING_RxNEG_IN_7
TxSTS1PL_7
S
IGNAL
N
AME
I/O
I/O
S
CMOS
T
TTL/
IGNAL
YPE
Transmit STS-3/STM-1 Telecom Bus Interface - Parity Input Pin -
Channel 3, DS3/E3 Framer Block LCV/RxNEG Input Pin - Chan-
nel - Channel 7:
The function of this input pin depends upon whether or not the STS-
3/STM-1 Telecom Bus Interface for Channel 3 has been enabled.
If STS-3/STM-1 Telecom Bus (Channel 3) has been enabled -
Transmit STS-3/STM-1 Telecom Bus Interface - Parity Input Pin:
This input pin can be configured to function as one of the following.
N
If STS-3/STM-1 Telecom Bus (Channel 0) is disabled - DS3/E3
Framer Block LCV/RxNEG Input Pin - Channel 7):
If the STS-3/STM-1 Telecom Bus (Channel 3) is disabled and if the
DS3/E3 Framer block (associated with Channel 7) is enabled then
this pin will function as either an LCV or an RxNEG input pin.
If Channel 7 is configured to operate in the Single-Rail Mode,
and if the Primary Frame Synchronizer block is configured to
operate in the Ingress Path - ING_LCV_IN_7 Input pin:
If the Primary Frame Synchronizer block (associated with Channel 7)
is configured to operate in the Ingress Path, and if Channel 7 is con-
figured to operate in the Single-Rail Mode, then this input pin will
function as the "LCV" (Line Code Violation) input pin. In this case,
the user should connect this particular input pin to the "LCV" output
pin of the corresponding DS3/E3/STS-1 LIU Channel.
If Channel 7 is configured to operate in the Dual-Rail Mode, and
if the Primary Frame Synchronizer block is configured to oper-
ate in the Ingress Path - ING_RxNEG_IN_7:
If the Primary Frame Synchronizer block (associated with Channel 7)
is configured to operate in the Ingress Path, and if Channel 7 is con-
figured to operate in the Dual-Rail Mode, then this input pin will func-
tion as the "RxNEG" (Negative Polarity Data) input pin. In this case,
the user should connect this particular input to the "RxNEG" output
pin of the corresponding DS3/E3/STS-1 LIU Channel.
N
OTE
OTE
1. The EVEN or ODD parity value of the bits which are input via
2. The EVEN or ODD parity value of the bits which are being
: Any one of these configuration selections can be made by
: This pin is inactive if the Primary Frame Synchronizer block
the ST3TXA_D_3[7:0] input pins.
input via the STS3TXA_D_3[7:0] input and the states of the
STS3TXA_PL_3 and STS3TXA_C1J1_3 input pins.
43
writing the appropriate value into the Interface Control
Register - Byte 3 register (Indirect Address = 0x00, 0x38),
(Direct Address = 0x0138).
(associated with Channel 7) is NOT configured to operate in
the Ingress Path.
D
ESCRIPTION
REV. 1.0.2