XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 151

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MICROPROCESSOR INTERFACE
XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
P
R23
V22
Y25
T23
T21
IN
#
PRD_L
PAS_L
PCS_L
PRDY_L
PDBEN_L
S
IGNAL
N
AME
I/O
O
I
I
I
I
S
CMOS READY or DTACK:
T
IGNAL
TTL
TTL
TTL
TTL
YPE
READ Strobe (Intel Mode):
If the Microprocessor Interface is operating in the Intel Mode, then this input
pin will function as the RD* (READ Strobe) input signal from the Micropro-
cessor. Once this active-low signal is asserted, then the Mapper/Framer will
place the contents of the addressed register (within the Mapper/Framer IC)
on the Microprocessor Bi-directional Data Bus (D[7:0]).
When this signal is negated, the Data Bus will be tri-stated.
Data Strobe (Motorola Mode).
If the Microprocessor Interface is operating in the Motorola Mode, then this
input will function as the DS* (Data Strobe) signal.
Address Latch Enable/Address Strobe:
This input pin is used to latch the address (present at the Microprocessor
Interface Address Bus pins (A[6:0]) into the Mapper/Framer Microprocessor
Interface block and to indicate the start of a READ or WRITE cycle. This
input pin is active-High, in the Intel Mode and active-Low in the Motorola
Mode.
Chip Select Input:
This active "Low" signal must be asserted in order to select the Micropro-
cessor Interface for READ and WRITE operations between the Micropro-
cessor and the Mapper/Framer on-chip registers and RAM locations.
This active-low output pin will function as the READY output when the
Microprocessor Interface is configured to operate in the Intel Mode; and will
function as the DTACK output, when the Microprocessor Interface is run-
ning in the Motorola Mode.
Intel Mode - READY output:
When the Mapper/Framer negates this output pin (e.g., toggles it "Low") it
indicates (to the Microprocessor) that the current READ or WRITE opera-
tion is to be extended until this signal is asserted (e.g., toggled "High").
Motorola Mode - DTACK (Data Transfer Acknowledge) Output:
The Mapper/Framer will assert this pin in order to inform the Microproces-
sor that the present READ or WRITE cycle is nearly complete. If the Map-
per/Framer requires that the current READ or WRITE cycle be extended,
then the Mapper/Framer will delay its assertion of this signal. The 68000
family of Microprocessors require this signal from its peripheral devices, in
order to quickly and properly complete a READ or WRITE cycle.
Bi-directional Data Bus Enable Input Pin:
If the Microprocessor Interface is operating in the Intel-I960 Mode, then this
input pin is used to enable the Bi-directional Data Bus.
Setting this input pin "Low" enables the Bi-directional Data bus.
Setting this input "High" tri-states the Bi-directional Data Bus.
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ESCRIPTION
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