XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 136

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RECEIVE TRANSPORT OVERHEAD INTERFACE
REV. 1.0.2
P
AB5
AA5
W4
IN
#
RxSDCC
RxSDCCVAL
RxE1F1E2VAL
S
IGNAL
N
AME
I/O
O
O
O
S
CMOS Receive - Section DCC Output Port - Output Pin:
CMOS Receive - Section DCC Output Port - DCC Value Indicator Output Pin:
CMOS Receive - Order Wire Output Port - E1F1E2 Value Indicator Output
T
IGNAL
YPE
This output pin, along with RxSDCCVAL and the RxTOHClk output pins
function as the Receive Section DCC output port of the XRT94L43.
This pin outputs the contents of the Section DCC (e.g., the D1, D2 and D3
bytes), within the incoming STS-12 data-stream. The Receive Section
DCC Output port will assert the RxSDCCVAL output pin, in order to indi-
cate that the data, residing on the RxSDCC output pin is a valid Section
DCC byte. The Receive Section DCC output port will update the RxSDC-
CVAL and the RxSDCC output pins upon the falling edge of the RxTOHClk
output pin. The Section DCC HDLC circuitry that is interfaced to this output
pin, the RxSDCCVAL and the RxTOHClk pins is suppose to do the follow-
ing.
1. It should continuously sample and monitor the state of the RxSDCCVAL
output pin upon the rising edge of RxTOHClk.
2. Anytime the Section DCC HDLC circuitry samples the RxSDCCVAL out-
put pin "High", it should sample and latch the contents of this output pin
(as a valid Section DCC bit) into the Section DCC HDLC circuitry.
This output pin, along with the RxTOHClk and the RxSDCC output pins
function as the Receive Section DCC output port of the XRT94L43.
This output pin pulses "High" coincident to when the Receive Section DCC
output port outputs a DCC bit via the RxSDCC output pin.
This output pin is updated upon the falling edge of RxTOHClk.
The Section DCC HDLC Controller circuitry that is interfaced to this output
pin, the RxSDCC and the RxTOHClk pins is suppose to do the following.
1. It should continuously sample and monitor the state of this output pin
upon the rising edge of RxTOHClk.
2. Anytime the Section DCC HDLC circuitry samples this output pin being
"High", it should sample and latch the data on the RxSDCC output pin (as
a valid Section DCC bit) into the Section DCC HDLC circuitry.
Pin:
This output pin, along with the RxTOHClk, RxE1F1E2FP, RxE1F1E2 and
RxTOHClk output pins function as the Receive - Order Wire Output Port of
the XRT94L43.
This output pin pulses "High" coincident to when the Receive - Order Wire
output port outputs the contents of an E1, F1 or E2 byte, via the
RxE1F1E2 output pin.
This output pin is updated upon the falling edge of RxTOHClk.
The Receive Order-Wire circuitry, that is interfaced to this output pin, the
RxE1F1E2 and the RxTOHClk pins is suppose to do the following.
1. It should continuously sample and monitor the state of this output pin
upon the rising edge of RxTOHClk.
2. Anytime the Receive Order-Wire circuitry samples this output pin being
"High", it should sample and latch the data on the RxE1F1E2 output pin
(as a valid Order-wire bit) into the Receive Order-Wire circuitry.
130
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
D
ESCRIPTION
XRT94L43